# Format:
#
# {=chip ids
#     fuse name | description | values....
#     ...more fuses...
# }

# ATmega 8u2, 16, 48, 88, 168, 328, 328p, 1284p, 128
{=avr:1e9389,avr:1e9403,avr:1e9205,avr:1e930a,avr:1e9406,avr:1e9514,avr:1e950f,avr:1e9705,avr:1e9702
    eesave | EEPROM memory is preserved through the Chip Erase. Default: Erase | 0b1=Erase | 0b0=Preserve
    lb | Memory lock bit (Default: No lock) | 0b11=No lock | 0b10=Disable write | 0b00=Disable read and write | 0b01=<reserved>
    blb0 | Boot lock bit (Default: No restrictions) | 0b11=No restrictions
    blb1 | Boot lock bit (Default: No restrictions) | 0b11=No restrictions
    wdton | Watchdog Timer always on (Default: Yes) | 0b1=No | 0b0=Yes
    spien | Enable SPI Serial program and Data downloading (default: enabled) | 0b0=Enabled | 0b1=Disabled
}

# ATmega 8u2, 16, 88, 168, 328, 328p, 1284p, 128
{=avr:1e9389,avr:1e9403,avr:1e930a,avr:1e9406,avr:1e9514,avr:1e950f,avr:1e9705,avr:1e9702 
    bootrst | Reset address (Default: Normal) | 0b1=Normal | 0b0=Bootloader
}

# ATmega 1284p, 128
{=avr:1e9705,avr:1e9702
    bootsz | Bootloader section size (default: 4096 words) | 0b11=512 words | 0b10=1024 words | 0b01=2048 words | 0b00=4096 words
}
# ATmega 16, 88, 168
{=avr:1e9403,avr:1e930a,avr:1e9406
    bootsz | Bootloader section size (default: 1024 words) | 0b11=128 words | 0b10=256 words | 0b01=512 words | 0b00=1024 words
}
# ATmega 328,328p
{=avr:1e9514,avr:1e950f
    bootsz | Bootloader section size (default: 2048 words) | 0b11=256 words | 0b10=512 words | 0b01=1024 words | 0b00=2048 words
}

# ATmega 16, 1284p, 128
{=avr:1e9403,avr:1e9705,avr:1e9702
    jtagen | Enable JTAG (default: enabled) | 0b1=Disabled | 0b0=Enabled
    ocden | Enable OCD (default: disable) | 0b1=Disabled | 0b0=Enabled
}

# ATmega16, 128
{=avr:1e9403,avr:1e9702
    boden | Brown-out Detector enable (default: disabled) | 0b1=Disabled | 0b0=Enabled
    ckopt | Oscillator options, see datasheet (default: max 8Mhz, LP) | 0b0=max 16Mhz, r-to-r | 0b1=max 8Mhz, LP
    sut+cksel | first 2b start-up time; next 4b clock source, see datasheet (default: IntRC 1Mhz 6ck+65ms) ||
        0b100001=IntRC 1Mhz 6ck+65ms | 0b010001=IntRC 1Mhz 6ck+4.1ms | 0b000001=IntRC 1Mhz 6ck | 0b110001=<reserved> ||
        0b100010=IntRC 2Mhz 6ck+65ms | 0b010010=IntRC 2Mhz 6ck+4.1ms | 0b000010=IntRC 2Mhz 6ck | 0b110010=<reserved> ||
        0b100011=IntRC 4Mhz 6ck+65ms | 0b010011=IntRC 4Mhz 6ck+4.1ms | 0b000011=IntRC 4Mhz 6ck | 0b110011=<reserved> ||
        0b100100=IntRC 8Mhz 6ck+65ms | 0b010100=IntRC 8Mhz 6ck+4.1ms | 0b000100=IntRC 8Mhz 6ck | 0b110100=<reserved> ||
        0b100000=Ext clock 6ck+65ms | 0b010000=Ext clock 6ck+4.1ms | 0b000000=Ext clock 6ck | 0b110000=<reserved> ||
        0b001010=XT 0.4-0.9Mhz 258ck+4.1ms | 0b011010=XT 0.4-0.9Mhz 258ck+65ms | 0b101010=XT 0.4-0.9Mhz 1Kck | 0b111010=XT 0.4-0.9Mhz 1Kck+4.1ms ||
        0b001011=XT 0.4-0.9Mhz 1Kck+65ms | 0b011011=XT 0.4-0.9Mhz 16Kck | 0b101011=XT 0.4-0.9Mhz 16Kck+4.1ms | 0b111011=XT 0.4-0.9Mhz 16Kck+65ms ||
        0b001100=XT 0.9-3.0Mhz 258ck+4.1ms | 0b011100=XT 0.9-3.0Mhz 258ck+65ms | 0b101100=XT 0.9-3.0Mhz 1Kck | 0b111100=XT 0.9-3.0Mhz 1Kck+4.1ms ||
        0b001101=XT 0.9-3.0Mhz 1Kck+65ms | 0b011101=XT 0.9-3.0Mhz 16Kck | 0b101101=XT 0.9-3.0Mhz 16Kck+4.1ms | 0b111101=XT 0.9-3.0Mhz 16Kck+65ms ||
        0b001110=XT 3.0-8.0Mhz 258ck+4.1ms | 0b011110=XT 3.0-8.0Mhz 258ck+65ms | 0b101110=XT 3.0-8.0Mhz 1Kck | 0b111110=XT 3.0-8.0Mhz 1Kck+4.1ms ||
        0b001111=XT 3.0-8.0Mhz 1Kck+65ms | 0b011111=XT 3.0-8.0Mhz 16Kck | 0b101111=XT 3.0-8.0Mhz 16Kck+4.1ms | 0b111111=XT 3.0-8.0Mhz 16Kck+65ms ||
        0b001001=LP XT 1Kck+4.1ms | 0b011001=LP XT 1Kck+65ms | 0b101001=LP XT 32Kck+65ms | 0b111001=<reserved> ||
        0b000101=ExtRC 0.1-0.9Mhz 18ck | 0b010101=ExtRC 0.1-0.9Mhz 18ck+4.1ms | 0b100101=ExtRC 0.1-0.9Mhz 18ck+65ms | 0b110101=ExtRC 0.1-0.9Mhz 6ck+4.1ms ||
        0b000110=ExtRC 0.9-3.0Mhz 18ck | 0b010110=ExtRC 0.9-3.0Mhz 18ck+4.1ms | 0b100110=ExtRC 0.9-3.0Mhz 18ck+65ms | 0b110110=ExtRC 0.9-3.0Mhz 6ck+4.1ms ||
        0b000111=ExtRC 3.0-8.0Mhz 18ck | 0b010111=ExtRC 3.0-8.0Mhz 18ck+4.1ms | 0b100111=ExtRC 3.0-8.0Mhz 18ck+65ms | 0b110111=ExtRC 3.0-8.0Mhz 6ck+4.1ms ||
        0b001000=ExtRC 8.0-12Mhz 18ck | 0b011000=ExtRC 8.0-12Mhz 18ck+4.1ms | 0b101000=ExtRC 8.0-12Mhz 18ck+65ms | 0b111000=ExtRC 8.0-12Mhz 6ck+4.1ms
}

# ATmega128
{=avr:1e9702
    bodlevel | Brown-out Detector trigger level. BODEN must be enabled! (default 2.6V) | 0b0=4.0V | 0b1=2.6V
    m103c | ATmega103 compatibility mode (default: enabled) | 0b1=Disabled | 0b0=Enabled
}

# ATmega 16
{=avr:1e9403
    bodlevel | Brown-out Detector trigger level. BODEN must be enabled! (default 2.7V) | 0b0=4.0V | 0b1=2.7V
}

# ATmega 48, 88, 168, 328, 328p, 1284p
{=avr:1e9205,avr:1e930a,avr:1e9406,avr:1e9514,avr:1e950f,avr:1e9705
    sut+cksel | first 2b start-up time; next 4b clock source, see datasheet (default: IntRC 8Mhz 6ck+65ms) ||
        0b000010=IntRC 8Mhz 6ck | 0b010010=IntRC 8Mhz 6ck+4.1ms | 0b100010=IntRC 8Mhz 6ck+65ms | 0b110010=<reserved> ||
        0b000000=Ext clock 6ck | 0b010000=Ext clock 6ck+4.1ms | 0b100000=Ext clock 6ck+65ms | 0b110000=<reserved> ||
        0b001000=XT 0.4-0.9Mhz 258ck+4.1ms | 0b011000=XT 0.4-0.9Mhz 258ck+65ms | 0b101000=XT 0.4-0.9Mhz 1Kck | 0b111000=XT 0.4-0.9Mhz 1Kck+4.1ms ||
        0b001001=XT 0.4-0.9Mhz 1Kck+65ms | 0b011001=XT 0.4-0.9Mhz 16Kck | 0b101001=XT 0.4-0.9Mhz 16Kck+4.1ms | 0b111001=XT 0.4-0.9Mhz 16Kck+65ms ||
        0b001010=XT 0.9-3.0Mhz 258ck+4.1ms | 0b011010=XT 0.9-3.0Mhz 258ck+65ms | 0b101010=XT 0.9-3.0Mhz 1Kck | 0b111010=XT 0.9-3.0Mhz 1Kck+4.1ms ||
        0b001011=XT 0.9-3.0Mhz 1Kck+65ms | 0b011011=XT 0.9-3.0Mhz 16Kck | 0b101011=XT 0.9-3.0Mhz 16Kck+4.1ms | 0b111011=XT 0.9-3.0Mhz 16Kck+65ms ||
        0b001100=XT 3.0-8.0Mhz 258ck+4.1ms | 0b011100=XT 3.0-8.0Mhz 258ck+65ms | 0b101100=XT 3.0-8.0Mhz 1Kck | 0b111100=XT 3.0-8.0Mhz 1Kck+4.1ms ||
        0b001101=XT 3.0-8.0Mhz 1Kck+65ms | 0b011101=XT 3.0-8.0Mhz 16Kck | 0b101101=XT 3.0-8.0Mhz 16Kck+4.1ms | 0b111101=XT 3.0-8.0Mhz 16Kck+65ms ||
        0b001110=XT 8.0-16.0Mhz 258ck+4.1ms | 0b011110=XT 8.0-16.0Mhz 258ck+65ms | 0b101110=XT 8.0-16.0Mhz 1Kck | 0b111110=XT 8.0-16.0Mhz 1Kck+4.1ms ||
        0b001111=XT 8.0-16.0Mhz 1Kck+65ms | 0b011111=XT 8.0-16.0Mhz 16Kck | 0b101111=XT 8.0-16.0Mhz 16Kck+4.1ms | 0b111111=XT 8.0-16.0Mhz 16Kck+65ms ||
        0b000110=Full swing 258ck+4.1ms | 0b010110=Full swing 258ck+65ms | 0b100110=Full swing 1Kck | 0b110110=Full swing 1Kck+4.1ms ||
        0b000111=Full swing 1Kck+65ms | 0b010111=Full swing 16Kck | 0b100111=Full swing 16Kck+4.1ms | 0b110111=Full swing 16Kck+65ms ||
        0b000100=LP XT 1Kck | 0b010100=LP XT 1Kck+4.1ms | 0b100100=LP XT 1Kck+65ms | 0b110100=<reserved> ||
        0b000101=LP XT 32Kck | 0b010101=LP XT 32Kck+4.1ms | 0b100101=LP XT 32Kck+65ms | 0b110101=<reserved> ||
        0b000011=Int 128kHz 6ck | 0b010011=Int 128kHz 6ck+4ms | 0b100011=Int 128kHz 6ck+65ms | 0b110011=<reserved> ||
        0b000001=<reserved> | 0b010001=<reserved> | 0b100001=<reserved> | 0b110001=<reserved>
    bodlevel | Brown-out Detector trigger level (default: Disabled) | 0b111=Disabled | 0b110=1.8V | 0b101=2.7V | 0b100=4.3V ||
            0b011=<reserved> | 0b010=<reserved> | 0b001=<reserved> | 0b000=<reserved>
}

# atmega8u2
{=avr:1e9389
    sut+cksel | first 2b start-up time; next 4b clock source, see datasheet (default: IntRC 8Mhz 6ck+65ms) ||
        0b000010=IntRC 8Mhz 6ck | 0b010010=IntRC 8Mhz 6ck+4.1ms | 0b100010=IntRC 8Mhz 6ck+65ms | 0b110010=<reserved> ||
        0b000000=Ext clock 6ck | 0b010000=Ext clock 6ck+4.1ms | 0b100000=Ext clock 6ck+65ms | 0b110000=<reserved> ||
        0b001000=LP XT 0.4-0.9Mhz 258ck+4.1ms | 0b011000=LP XT 0.4-0.9Mhz 258ck+65ms | 0b101000=LP XT 0.4-0.9Mhz 1Kck | 0b111000=LP XT 0.4-0.9Mhz 1Kck+4.1ms ||
        0b001001=LP XT 0.4-0.9Mhz 1Kck+65ms | 0b011001=LP XT 0.4-0.9Mhz 16Kck | 0b101001=LP XT 0.4-0.9Mhz 16Kck+4.1ms | 0b111001=LP XT 0.4-0.9Mhz 16Kck+65ms ||
        0b001010=LP XT 0.9-3.0Mhz 258ck+4.1ms | 0b011010=LP XT 0.9-3.0Mhz 258ck+65ms | 0b101010=LP XT 0.9-3.0Mhz 1Kck | 0b111010=LP XT 0.9-3.0Mhz 1Kck+4.1ms ||
        0b001011=LP XT 0.9-3.0Mhz 1Kck+65ms | 0b011011=LP XT 0.9-3.0Mhz 16Kck | 0b101011=LP XT 0.9-3.0Mhz 16Kck+4.1ms | 0b111011=LP XT 0.9-3.0Mhz 16Kck+65ms ||
        0b001100=LP XT 3.0-8.0Mhz 258ck+4.1ms | 0b011100=LP XT 3.0-8.0Mhz 258ck+65ms | 0b101100=LP XT 3.0-8.0Mhz 1Kck | 0b111100=LP XT 3.0-8.0Mhz 1Kck+4.1ms ||
        0b001101=LP XT 3.0-8.0Mhz 1Kck+65ms | 0b011101=LP XT 3.0-8.0Mhz 16Kck | 0b101101=LP XT 3.0-8.0Mhz 16Kck+4.1ms | 0b111101=LP XT 3.0-8.0Mhz 16Kck+65ms ||
        0b001110=LP XT 8.0-16.0Mhz 258ck+4.1ms | 0b011110=LP XT 8.0-16.0Mhz 258ck+65ms | 0b101110=LP XT 8.0-16.0Mhz 1Kck | 0b111110=LP XT 8.0-16.0Mhz 1Kck+4.1ms ||
        0b001111=LP XT 8.0-16.0Mhz 1Kck+65ms | 0b011111=LP XT 8.0-16.0Mhz 16Kck | 0b101111=LP XT 8.0-16.0Mhz 16Kck+4.1ms | 0b111111=LP XT 8.0-16.0Mhz 16Kck+65ms ||
        0b000110=Full swing 258ck+4.1ms | 0b010110=Full swing 258ck+65ms | 0b100110=Full swing 1Kck | 0b110110=Full swing 1Kck+4.1ms ||
        0b000111=Full swing 1Kck+65ms | 0b010111=Full swing 16Kck | 0b100111=Full swing 16Kck+4.1ms | 0b110111=Full swing 16Kck+65ms ||
        0b000100=<reserved> | 0b010100=<reserved> | 0b100100=<reserved> | 0b110100=<reserved> ||
        0b000101=<reserved> | 0b010101=<reserved> | 0b100101=<reserved> | 0b110101=<reserved> ||
        0b000011=<reserved> | 0b010011=<reserved> | 0b100011=<reserved> | 0b110011=<reserved> ||
        0b000001=<reserved> | 0b010001=<reserved> | 0b100001=<reserved> | 0b110001=<reserved>
    bodlevel | Brown-out Detector trigger level (default: Disabled) | 0b111=Disabled | 0b110=2.7V ||
        0b101=<reserved> | 0b100=3.0V | 0b011=3.5V | 0b010=<reserved> | 0b001=4.0V | 0b000=4.3V
    hwbe | Enable hardware boot (default: enable) | 0b1=Disabled | 0b0=Enabled
    rstdsbl | Disable reset pin (default: disabled) | 0b1=Disabled | 0b0=Enabled
    bootsz | Bootloader section size (default: 2048 words) | 0b11=256 words | 0b10=512 words | 0b01=1024 words | 0b00=2048 words
}

# ATmega 48, 88, 168, 328, 328p, 1284p, 8u2
{=avr:1e9205,avr:1e930a,avr:1e9406,avr:1e9514,avr:1e950f,avr:1e9705,avr:1e9389
    ckout | Output system clock to CLKO pin (default: disabled) | 0b1=Disabled | 0b0=Enabled
    ckdiv8 | Divide system click by 8 (default: enabled) | 0b1=Disabled | 0b0=Enabled
    dwen | Enable debugWIRE (default: disabled) | 0b1=Disabled | 0b0=Enabled
    rstdisbl | Disable external reset (default: disabled) | 0b1=Disabled | 0b0=Enabled
    selfprgen | Enable self programming (default: disabled) | 0b01=Disabled | 0b0=Enabled
}

# atxmega128a, atxmega64a, atxmega32a, atxmega16a
{=avr:1e9746,avr:1e9646,avr:1e9541,avr:1e9441
    jtaguid | JTAG user id (default: 0b00000000)
    wdwper | Watchdog window timeout period (default: 8clk) | 0b0000=8clk | 0b0001=16clk | 0b0010=32clk | 0b0011=64clk | 0b0100=125clk | 0b0101=250clk ||
        0b0110=500clk | 0b0111=1Kclk | 0b1000=2Kclk | 0b1001=4Kclk | 0b1010=8Kclk | 0b1011=<reserved> | 0b1100=<reserved> | 0b1101=<reserved> | 0b1110=<reserved> | 0b1111=<reserved>
    wdper | Watchdog timeout period (default: 8clk) | 0b0000=8clk | 0b0001=16clk | 0b0010=32clk | 0b0011=64clk | 0b0100=125clk | 0b0101=250clk ||
        0b0110=500clk | 0b0111=1Kclk | 0b1000=2Kclk | 0b1001=4Kclk | 0b1010=8Kclk | 0b1011=<reserved> | 0b1100=<reserved> | 0b1101=<reserved> | 0b1110=<reserved> | 0b1111=<reserved>
    bootrst | Reset address (Default: Normal) | 0b1=Normal | 0b0=Bootloader
    bodpd | BOD operation in power-down mode (Default: BOD Disabled) | 0b00=<reserved> | 0b01=BOD in sampled mode | 0b10=BOD continuously | 0b11=BOD Disabled
    rstdisbl | External reset disable (default: disabled) | 0b1=Disabled | 0b0=Enabled
    startuptime | Start-up time (default: 0 cycles) | 0b00=64 cycles | 0b01=4 cycles | 0b10=<reserved> | 0b11=0 cycles
    wdlock | Watchdog timer lock (default: Not locked) | 0b1=Not locked | 0b0=Locked
    jtagen | JTAG enabled (default: enabled) | 0b1=Disabled | 0b0=Enabled
    bodact | BOD operation in active mode (Read only) | 0b00=<reserved> | 0b01=BOD in sampled | 0b10=BOD continuously | 0b11=BOD Disabled
    eesave | Preverve EEPROM trough the Chip erase | 0b1=Erase | 0b0=Preserve
    bodlevel | Brown out detection voltage level | 0b111=1.6V | 0b110=1.8V | 0b101=2.0V | 0b100=2.2V | 0b011=2.4V | 0b010=2.7V | 0b001=2.9V | 0b000=3.2V
    blbb | Boot lock bit boot loader section. See datasheet. (default: NOLOCK) | 0b11=NOLOCK | 0b10=WLOCK | 0b01=RLOCK | 0b00=RWLOCK
    blba | Boot lock bit Application section. See datasheet. (default: NOLOCK) | 0b11=NOLOCK | 0b10=WLOCK | 0b01=RLOCK | 0b00=RWLOCK
    blbat | Boot lock bit Application table section. See datasheet. (default: NOLOCK) | 0b11=NOLOCK | 0b10=WLOCK | 0b01=RLOCK | 0b00=RWLOCK
    lb | Lock bits. See datasheet (default: NOLOCK3) | 0b11=NOLOCK3 | 0b10=WLOCK | 0b00=RWLOCK | 0b01=<reserved>
}
