; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\STM324xG_EVAL\system_stm32f4xx.o --asm_dir=.\STM324xG_EVAL\ --list_dir=.\STM324xG_EVAL\ --depend=.\STM324xG_EVAL\system_stm32f4xx.d --cpu=Cortex-M4.fp --apcs=interwork -O0 -Otime -I..\ -I..\..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\..\Utilities\STM32_EVAL\Common -I..\..\..\Utilities\STM32_EVAL\STM3240_41_G_EVAL -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F4xx -D__MICROLIB -DUSE_STM324xG_EVAL -DSTM32F4XX -DUSE_STDPERIPH_DRIVER --omf_browse=.\STM324xG_EVAL\system_stm32f4xx.crf ..\system_stm32f4xx.c]
                          THUMB

                          AREA ||i.SetSysClock||, CODE, READONLY, ALIGN=2

                  SetSysClock PROC
;;;340      */
;;;341    static void SetSysClock(void)
000000  4822              LDR      r0,|L1.140|
;;;342    {
;;;343    /******************************************************************************/
;;;344    /*            PLL (clocked by HSI) used as System clock source                */
;;;345    /******************************************************************************/
;;;346    
;;;347      /* At this stage the HSI is already enabled and used as System clock source */
;;;348    
;;;349        /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
;;;350        RCC->APB1ENR |= RCC_APB1ENR_PWREN;
000002  6800              LDR      r0,[r0,#0]
000004  f0405080          ORR      r0,r0,#0x10000000
000008  4920              LDR      r1,|L1.140|
00000a  6008              STR      r0,[r1,#0]
;;;351        PWR->CR |= PWR_CR_VOS;
00000c  4820              LDR      r0,|L1.144|
00000e  6800              LDR      r0,[r0,#0]
000010  f4404080          ORR      r0,r0,#0x4000
000014  491e              LDR      r1,|L1.144|
000016  6008              STR      r0,[r1,#0]
;;;352    
;;;353      /* HCLK = SYSCLK / 1*/
;;;354      RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
000018  481c              LDR      r0,|L1.140|
00001a  3838              SUBS     r0,r0,#0x38
00001c  6800              LDR      r0,[r0,#0]
00001e  491b              LDR      r1,|L1.140|
000020  3938              SUBS     r1,r1,#0x38
000022  6008              STR      r0,[r1,#0]
;;;355          
;;;356      /* PCLK2 = HCLK / 2*/
;;;357      RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
000024  4608              MOV      r0,r1
000026  6800              LDR      r0,[r0,#0]
000028  f4404000          ORR      r0,r0,#0x8000
00002c  6008              STR      r0,[r1,#0]
;;;358        
;;;359      /* PCLK1 = HCLK / 1*/
;;;360      RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
00002e  4608              MOV      r0,r1
000030  6800              LDR      r0,[r0,#0]
000032  f44050a0          ORR      r0,r0,#0x1400
000036  6008              STR      r0,[r1,#0]
;;;361    
;;;362      /* Configure the main PLL */
;;;363      RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
000038  4816              LDR      r0,|L1.148|
00003a  1f09              SUBS     r1,r1,#4
00003c  6008              STR      r0,[r1,#0]
;;;364                     (RCC_PLLCFGR_PLLSRC_HSI) | (PLL_Q << 24);
;;;365    
;;;366      /* Enable the main PLL */
;;;367      RCC->CR |= RCC_CR_PLLON;
00003e  1f08              SUBS     r0,r1,#4
000040  6800              LDR      r0,[r0,#0]
000042  f0407080          ORR      r0,r0,#0x1000000
000046  1f09              SUBS     r1,r1,#4
000048  6008              STR      r0,[r1,#0]
;;;368    
;;;369      /* Wait till the main PLL is ready */
;;;370      while((RCC->CR & RCC_CR_PLLRDY) == 0)
00004a  bf00              NOP      
                  |L1.76|
00004c  480f              LDR      r0,|L1.140|
00004e  3840              SUBS     r0,r0,#0x40
000050  6800              LDR      r0,[r0,#0]
000052  f0107f00          TST      r0,#0x2000000
000056  d0f9              BEQ      |L1.76|
;;;371      {
;;;372      }
;;;373       
;;;374      /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
;;;375      FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
000058  f2406005          MOV      r0,#0x605
00005c  490e              LDR      r1,|L1.152|
00005e  6008              STR      r0,[r1,#0]
;;;376    
;;;377      /* Select the main PLL as system clock source */
;;;378      RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
000060  480a              LDR      r0,|L1.140|
000062  3838              SUBS     r0,r0,#0x38
000064  6800              LDR      r0,[r0,#0]
000066  f0200003          BIC      r0,r0,#3
00006a  4908              LDR      r1,|L1.140|
00006c  3938              SUBS     r1,r1,#0x38
00006e  6008              STR      r0,[r1,#0]
;;;379      RCC->CFGR |= RCC_CFGR_SW_PLL;
000070  4608              MOV      r0,r1
000072  6800              LDR      r0,[r0,#0]
000074  f0400002          ORR      r0,r0,#2
000078  6008              STR      r0,[r1,#0]
;;;380    
;;;381      /* Wait till the main PLL is used as system clock source */
;;;382      while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
00007a  bf00              NOP      
                  |L1.124|
00007c  4803              LDR      r0,|L1.140|
00007e  3838              SUBS     r0,r0,#0x38
000080  6800              LDR      r0,[r0,#0]
000082  f000000c          AND      r0,r0,#0xc
000086  2808              CMP      r0,#8
000088  d1f8              BNE      |L1.124|
;;;383      {
;;;384      }
;;;385    }
00008a  4770              BX       lr
;;;386    
                          ENDP

                  |L1.140|
                          DCD      0x40023840
                  |L1.144|
                          DCD      0x40007000
                  |L1.148|
                          DCD      0x07005410
                  |L1.152|
                          DCD      0x40023c00

                          AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2

                  SystemCoreClockUpdate PROC
;;;284      */
;;;285    void SystemCoreClockUpdate(void)
000000  b530              PUSH     {r4,r5,lr}
;;;286    {
;;;287      uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
000002  2000              MOVS     r0,#0
000004  2200              MOVS     r2,#0
000006  2302              MOVS     r3,#2
000008  4684              MOV      r12,r0
00000a  2102              MOVS     r1,#2
;;;288      
;;;289      /* Get SYSCLK source -------------------------------------------------------*/
;;;290      tmp = RCC->CFGR & RCC_CFGR_SWS;
00000c  4c28              LDR      r4,|L2.176|
00000e  6824              LDR      r4,[r4,#0]
000010  f004000c          AND      r0,r4,#0xc
;;;291    
;;;292      switch (tmp)
000014  b120              CBZ      r0,|L2.32|
000016  2804              CMP      r0,#4
000018  d006              BEQ      |L2.40|
00001a  2808              CMP      r0,#8
00001c  d136              BNE      |L2.140|
00001e  e007              B        |L2.48|
                  |L2.32|
;;;293      {
;;;294        case 0x00:  /* HSI used as system clock source */
;;;295          SystemCoreClock = HSI_VALUE;
000020  4c24              LDR      r4,|L2.180|
000022  4d25              LDR      r5,|L2.184|
000024  602c              STR      r4,[r5,#0]  ; SystemCoreClock
;;;296          break;
000026  e035              B        |L2.148|
                  |L2.40|
;;;297        case 0x04:  /* HSE used as system clock source */
;;;298          SystemCoreClock = HSE_VALUE;
000028  4c24              LDR      r4,|L2.188|
00002a  4d23              LDR      r5,|L2.184|
00002c  602c              STR      r4,[r5,#0]  ; SystemCoreClock
;;;299          break;
00002e  e031              B        |L2.148|
                  |L2.48|
;;;300        case 0x08:  /* PLL used as system clock source */
;;;301    
;;;302          /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
;;;303             SYSCLK = PLL_VCO / PLL_P
;;;304             */    
;;;305          pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
000030  4c1f              LDR      r4,|L2.176|
000032  1f24              SUBS     r4,r4,#4
000034  6824              LDR      r4,[r4,#0]
000036  f3c45c80          UBFX     r12,r4,#22,#1
;;;306          pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
00003a  4c1d              LDR      r4,|L2.176|
00003c  1f24              SUBS     r4,r4,#4
00003e  6824              LDR      r4,[r4,#0]
000040  f004013f          AND      r1,r4,#0x3f
;;;307          
;;;308          if (pllsource != 0)
000044  f1bc0f00          CMP      r12,#0
000048  d00a              BEQ      |L2.96|
;;;309          {
;;;310            /* HSE used as PLL clock source */
;;;311            pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
00004a  4c1c              LDR      r4,|L2.188|
00004c  fbb4f4f1          UDIV     r4,r4,r1
000050  4d17              LDR      r5,|L2.176|
000052  1f2d              SUBS     r5,r5,#4
000054  682d              LDR      r5,[r5,#0]
000056  f3c51588          UBFX     r5,r5,#6,#9
00005a  fb04f205          MUL      r2,r4,r5
00005e  e009              B        |L2.116|
                  |L2.96|
;;;312          }
;;;313          else
;;;314          {
;;;315            /* HSI used as PLL clock source */
;;;316            pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
000060  4c14              LDR      r4,|L2.180|
000062  fbb4f4f1          UDIV     r4,r4,r1
000066  4d12              LDR      r5,|L2.176|
000068  1f2d              SUBS     r5,r5,#4
00006a  682d              LDR      r5,[r5,#0]
00006c  f3c51588          UBFX     r5,r5,#6,#9
000070  fb04f205          MUL      r2,r4,r5
                  |L2.116|
;;;317          }
;;;318    
;;;319          pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
000074  4c0e              LDR      r4,|L2.176|
000076  1f24              SUBS     r4,r4,#4
000078  6824              LDR      r4,[r4,#0]
00007a  f3c44401          UBFX     r4,r4,#16,#2
00007e  1c64              ADDS     r4,r4,#1
000080  0063              LSLS     r3,r4,#1
;;;320          SystemCoreClock = pllvco/pllp;
000082  fbb2f4f3          UDIV     r4,r2,r3
000086  4d0c              LDR      r5,|L2.184|
000088  602c              STR      r4,[r5,#0]  ; SystemCoreClock
;;;321          break;
00008a  e003              B        |L2.148|
                  |L2.140|
;;;322        default:
;;;323          SystemCoreClock = HSI_VALUE;
00008c  4c09              LDR      r4,|L2.180|
00008e  4d0a              LDR      r5,|L2.184|
000090  602c              STR      r4,[r5,#0]  ; SystemCoreClock
;;;324          break;
000092  bf00              NOP      
                  |L2.148|
000094  bf00              NOP                            ;296
;;;325      }
;;;326      /* Compute HCLK frequency --------------------------------------------------*/
;;;327      /* Get HCLK prescaler */
;;;328      tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
000096  4c06              LDR      r4,|L2.176|
000098  6824              LDR      r4,[r4,#0]
00009a  f3c41403          UBFX     r4,r4,#4,#4
00009e  4d08              LDR      r5,|L2.192|
0000a0  5d28              LDRB     r0,[r5,r4]
;;;329      /* HCLK frequency */
;;;330      SystemCoreClock >>= tmp;
0000a2  4c05              LDR      r4,|L2.184|
0000a4  6824              LDR      r4,[r4,#0]  ; SystemCoreClock
0000a6  40c4              LSRS     r4,r4,r0
0000a8  4d03              LDR      r5,|L2.184|
0000aa  602c              STR      r4,[r5,#0]  ; SystemCoreClock
;;;331    }
0000ac  bd30              POP      {r4,r5,pc}
;;;332    
                          ENDP

0000ae  0000              DCW      0x0000
                  |L2.176|
                          DCD      0x40023808
                  |L2.180|
                          DCD      0x00f42400
                  |L2.184|
                          DCD      SystemCoreClock
                  |L2.188|
                          DCD      0x017d7840
                  |L2.192|
                          DCD      AHBPrescTable

                          AREA ||i.SystemInit||, CODE, READONLY, ALIGN=2

                  SystemInit PROC
;;;207      */
;;;208    void SystemInit(void)
000000  b510              PUSH     {r4,lr}
;;;209    {
;;;210      /* FPU settings ------------------------------------------------------------*/
;;;211      #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
;;;212        SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
000002  4815              LDR      r0,|L3.88|
000004  6800              LDR      r0,[r0,#0]
000006  f4400070          ORR      r0,r0,#0xf00000
00000a  4913              LDR      r1,|L3.88|
00000c  6008              STR      r0,[r1,#0]
;;;213      #endif
;;;214      /* Reset the RCC clock configuration to the default reset state ------------*/
;;;215      /* Set HSION bit */
;;;216      RCC->CR |= (uint32_t)0x00000001;
00000e  4813              LDR      r0,|L3.92|
000010  6800              LDR      r0,[r0,#0]
000012  f0400001          ORR      r0,r0,#1
000016  4911              LDR      r1,|L3.92|
000018  6008              STR      r0,[r1,#0]
;;;217    
;;;218      /* Reset CFGR register */
;;;219      RCC->CFGR = 0x00000000;
00001a  2000              MOVS     r0,#0
00001c  490f              LDR      r1,|L3.92|
00001e  3108              ADDS     r1,r1,#8
000020  6008              STR      r0,[r1,#0]
;;;220    
;;;221      /* Reset HSEON, CSSON and PLLON bits */
;;;222      RCC->CR &= (uint32_t)0xFEF6FFFF;
000022  480e              LDR      r0,|L3.92|
000024  6800              LDR      r0,[r0,#0]
000026  490e              LDR      r1,|L3.96|
000028  4008              ANDS     r0,r0,r1
00002a  490c              LDR      r1,|L3.92|
00002c  6008              STR      r0,[r1,#0]
;;;223    
;;;224      /* Reset PLLCFGR register */
;;;225      RCC->PLLCFGR = 0x24003010;
00002e  480d              LDR      r0,|L3.100|
000030  1d09              ADDS     r1,r1,#4
000032  6008              STR      r0,[r1,#0]
;;;226    
;;;227      /* Reset HSEBYP bit */
;;;228      RCC->CR &= (uint32_t)0xFFFBFFFF;
000034  1f08              SUBS     r0,r1,#4
000036  6800              LDR      r0,[r0,#0]
000038  f4202080          BIC      r0,r0,#0x40000
00003c  1f09              SUBS     r1,r1,#4
00003e  6008              STR      r0,[r1,#0]
;;;229    
;;;230      /* Disable all interrupts */
;;;231      RCC->CIR = 0x00000000;
000040  2000              MOVS     r0,#0
000042  4906              LDR      r1,|L3.92|
000044  310c              ADDS     r1,r1,#0xc
000046  6008              STR      r0,[r1,#0]
;;;232    
;;;233    #ifdef DATA_IN_ExtSRAM
;;;234      SystemInit_ExtMemCtl(); 
;;;235    #endif /* DATA_IN_ExtSRAM */
;;;236             
;;;237      /* Configure the System clock source, PLL Multiplier and Divider factors, 
;;;238         AHB/APBx prescalers and Flash settings ----------------------------------*/
;;;239      SetSysClock();
000048  f7fffffe          BL       SetSysClock
;;;240    
;;;241      /* Configure the Vector Table location add offset address ------------------*/
;;;242    #ifdef VECT_TAB_SRAM
;;;243      SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
;;;244    #else
;;;245      SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
00004c  f04f6000          MOV      r0,#0x8000000
000050  4901              LDR      r1,|L3.88|
000052  3980              SUBS     r1,r1,#0x80
000054  6008              STR      r0,[r1,#0]
;;;246    #endif
;;;247    }
000056  bd10              POP      {r4,pc}
;;;248    
                          ENDP

                  |L3.88|
                          DCD      0xe000ed88
                  |L3.92|
                          DCD      0x40023800
                  |L3.96|
                          DCD      0xfef6ffff
                  |L3.100|
                          DCD      0x24003010

                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x0a037a00
                  AHBPrescTable
000004  00000000          DCB      0x00,0x00,0x00,0x00
000008  00000000          DCB      0x00,0x00,0x00,0x00
00000c  01020304          DCB      0x01,0x02,0x03,0x04
000010  06070809          DCB      0x06,0x07,0x08,0x09

;*** Start embedded assembler ***

#line 1 "..\\system_stm32f4xx.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___18_system_stm32f4xx_c_5d646a67____REV16|
#line 114 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___18_system_stm32f4xx_c_5d646a67____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___18_system_stm32f4xx_c_5d646a67____REVSH|
#line 128
|__asm___18_system_stm32f4xx_c_5d646a67____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
