; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\STM324xG_EVAL\stm32f4xx_tim.o --asm_dir=.\STM324xG_EVAL\ --list_dir=.\STM324xG_EVAL\ --depend=.\STM324xG_EVAL\stm32f4xx_tim.d --cpu=Cortex-M4.fp --apcs=interwork -O0 -Otime -I..\ -I..\..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\..\Utilities\STM32_EVAL\Common -I..\..\..\Utilities\STM32_EVAL\STM3240_41_G_EVAL -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F4xx -D__MICROLIB -DUSE_STM324xG_EVAL -DSTM32F4XX -DUSE_STDPERIPH_DRIVER --omf_browse=.\STM324xG_EVAL\stm32f4xx_tim.crf ..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_tim.c]
                          THUMB

                          AREA ||i.TI1_Config||, CODE, READONLY, ALIGN=1

                  TI1_Config PROC
;;;3190     */
;;;3191   static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000  b570              PUSH     {r4-r6,lr}
;;;3192                          uint16_t TIM_ICFilter)
;;;3193   {
000002  468c              MOV      r12,r1
000004  4614              MOV      r4,r2
;;;3194     uint16_t tmpccmr1 = 0, tmpccer = 0;
000006  2100              MOVS     r1,#0
000008  2200              MOVS     r2,#0
;;;3195   
;;;3196     /* Disable the Channel 1: Reset the CC1E Bit */
;;;3197     TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
00000a  8c05              LDRH     r5,[r0,#0x20]
00000c  f64f76fe          MOV      r6,#0xfffe
000010  4035              ANDS     r5,r5,r6
000012  8405              STRH     r5,[r0,#0x20]
;;;3198     tmpccmr1 = TIMx->CCMR1;
000014  8b01              LDRH     r1,[r0,#0x18]
;;;3199     tmpccer = TIMx->CCER;
000016  8c02              LDRH     r2,[r0,#0x20]
;;;3200   
;;;3201     /* Select the Input and set the filter */
;;;3202     tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
000018  f64f750c          MOV      r5,#0xff0c
00001c  4029              ANDS     r1,r1,r5
;;;3203     tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
00001e  051d              LSLS     r5,r3,#20
000020  ea444515          ORR      r5,r4,r5,LSR #16
000024  4329              ORRS     r1,r1,r5
;;;3204   
;;;3205     /* Select the Polarity and set the CC1E Bit */
;;;3206     tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
000026  f64f75f5          MOV      r5,#0xfff5
00002a  402a              ANDS     r2,r2,r5
;;;3207     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
00002c  f04c0501          ORR      r5,r12,#1
000030  432a              ORRS     r2,r2,r5
;;;3208   
;;;3209     /* Write to TIMx CCMR1 and CCER registers */
;;;3210     TIMx->CCMR1 = tmpccmr1;
000032  8301              STRH     r1,[r0,#0x18]
;;;3211     TIMx->CCER = tmpccer;
000034  8402              STRH     r2,[r0,#0x20]
;;;3212   }
000036  bd70              POP      {r4-r6,pc}
;;;3213   
                          ENDP


                          AREA ||i.TI2_Config||, CODE, READONLY, ALIGN=1

                  TI2_Config PROC
;;;3231     */
;;;3232   static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000  b5f0              PUSH     {r4-r7,lr}
;;;3233                          uint16_t TIM_ICFilter)
;;;3234   {
000002  460c              MOV      r4,r1
000004  4615              MOV      r5,r2
;;;3235     uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
000006  2100              MOVS     r1,#0
000008  2200              MOVS     r2,#0
00000a  468c              MOV      r12,r1
;;;3236   
;;;3237     /* Disable the Channel 2: Reset the CC2E Bit */
;;;3238     TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
00000c  8c06              LDRH     r6,[r0,#0x20]
00000e  f64f77ef          MOV      r7,#0xffef
000012  403e              ANDS     r6,r6,r7
000014  8406              STRH     r6,[r0,#0x20]
;;;3239     tmpccmr1 = TIMx->CCMR1;
000016  8b01              LDRH     r1,[r0,#0x18]
;;;3240     tmpccer = TIMx->CCER;
000018  8c02              LDRH     r2,[r0,#0x20]
;;;3241     tmp = (uint16_t)(TIM_ICPolarity << 4);
00001a  0526              LSLS     r6,r4,#20
00001c  ea4f4c16          LSR      r12,r6,#16
;;;3242   
;;;3243     /* Select the Input and set the filter */
;;;3244     tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
000020  f64046ff          MOV      r6,#0xcff
000024  4031              ANDS     r1,r1,r6
;;;3245     tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
000026  071e              LSLS     r6,r3,#28
000028  ea414116          ORR      r1,r1,r6,LSR #16
;;;3246     tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
00002c  062e              LSLS     r6,r5,#24
00002e  ea414116          ORR      r1,r1,r6,LSR #16
;;;3247   
;;;3248     /* Select the Polarity and set the CC2E Bit */
;;;3249     tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
000032  f64f765f          MOV      r6,#0xff5f
000036  4032              ANDS     r2,r2,r6
;;;3250     tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
000038  f04c0610          ORR      r6,r12,#0x10
00003c  4332              ORRS     r2,r2,r6
;;;3251   
;;;3252     /* Write to TIMx CCMR1 and CCER registers */
;;;3253     TIMx->CCMR1 = tmpccmr1 ;
00003e  8301              STRH     r1,[r0,#0x18]
;;;3254     TIMx->CCER = tmpccer;
000040  8402              STRH     r2,[r0,#0x20]
;;;3255   }
000042  bdf0              POP      {r4-r7,pc}
;;;3256   
                          ENDP


                          AREA ||i.TI3_Config||, CODE, READONLY, ALIGN=1

                  TI3_Config PROC
;;;3273     */
;;;3274   static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000  b5f0              PUSH     {r4-r7,lr}
;;;3275                          uint16_t TIM_ICFilter)
;;;3276   {
000002  460c              MOV      r4,r1
000004  4615              MOV      r5,r2
;;;3277     uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
000006  2100              MOVS     r1,#0
000008  2200              MOVS     r2,#0
00000a  468c              MOV      r12,r1
;;;3278   
;;;3279     /* Disable the Channel 3: Reset the CC3E Bit */
;;;3280     TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
00000c  8c06              LDRH     r6,[r0,#0x20]
00000e  f64f67ff          MOV      r7,#0xfeff
000012  403e              ANDS     r6,r6,r7
000014  8406              STRH     r6,[r0,#0x20]
;;;3281     tmpccmr2 = TIMx->CCMR2;
000016  8b81              LDRH     r1,[r0,#0x1c]
;;;3282     tmpccer = TIMx->CCER;
000018  8c02              LDRH     r2,[r0,#0x20]
;;;3283     tmp = (uint16_t)(TIM_ICPolarity << 8);
00001a  0626              LSLS     r6,r4,#24
00001c  ea4f4c16          LSR      r12,r6,#16
;;;3284   
;;;3285     /* Select the Input and set the filter */
;;;3286     tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
000020  f64f760c          MOV      r6,#0xff0c
000024  4031              ANDS     r1,r1,r6
;;;3287     tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
000026  051e              LSLS     r6,r3,#20
000028  ea454616          ORR      r6,r5,r6,LSR #16
00002c  4331              ORRS     r1,r1,r6
;;;3288   
;;;3289     /* Select the Polarity and set the CC3E Bit */
;;;3290     tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
00002e  f24f56ff          MOV      r6,#0xf5ff
000032  4032              ANDS     r2,r2,r6
;;;3291     tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
000034  f44c7680          ORR      r6,r12,#0x100
000038  4332              ORRS     r2,r2,r6
;;;3292   
;;;3293     /* Write to TIMx CCMR2 and CCER registers */
;;;3294     TIMx->CCMR2 = tmpccmr2;
00003a  8381              STRH     r1,[r0,#0x1c]
;;;3295     TIMx->CCER = tmpccer;
00003c  8402              STRH     r2,[r0,#0x20]
;;;3296   }
00003e  bdf0              POP      {r4-r7,pc}
;;;3297   
                          ENDP


                          AREA ||i.TI4_Config||, CODE, READONLY, ALIGN=1

                  TI4_Config PROC
;;;3314     */
;;;3315   static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000  b5f0              PUSH     {r4-r7,lr}
;;;3316                          uint16_t TIM_ICFilter)
;;;3317   {
000002  460c              MOV      r4,r1
000004  4615              MOV      r5,r2
;;;3318     uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
000006  2100              MOVS     r1,#0
000008  2200              MOVS     r2,#0
00000a  468c              MOV      r12,r1
;;;3319   
;;;3320     /* Disable the Channel 4: Reset the CC4E Bit */
;;;3321     TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
00000c  8c06              LDRH     r6,[r0,#0x20]
00000e  f64e77ff          MOV      r7,#0xefff
000012  403e              ANDS     r6,r6,r7
000014  8406              STRH     r6,[r0,#0x20]
;;;3322     tmpccmr2 = TIMx->CCMR2;
000016  8b81              LDRH     r1,[r0,#0x1c]
;;;3323     tmpccer = TIMx->CCER;
000018  8c02              LDRH     r2,[r0,#0x20]
;;;3324     tmp = (uint16_t)(TIM_ICPolarity << 12);
00001a  0726              LSLS     r6,r4,#28
00001c  ea4f4c16          LSR      r12,r6,#16
;;;3325   
;;;3326     /* Select the Input and set the filter */
;;;3327     tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
000020  f64046ff          MOV      r6,#0xcff
000024  4031              ANDS     r1,r1,r6
;;;3328     tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
000026  062e              LSLS     r6,r5,#24
000028  ea414116          ORR      r1,r1,r6,LSR #16
;;;3329     tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
00002c  071e              LSLS     r6,r3,#28
00002e  ea414116          ORR      r1,r1,r6,LSR #16
;;;3330   
;;;3331     /* Select the Polarity and set the CC4E Bit */
;;;3332     tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
000032  f64576ff          MOV      r6,#0x5fff
000036  4032              ANDS     r2,r2,r6
;;;3333     tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
000038  f44c5680          ORR      r6,r12,#0x1000
00003c  4332              ORRS     r2,r2,r6
;;;3334   
;;;3335     /* Write to TIMx CCMR2 and CCER registers */
;;;3336     TIMx->CCMR2 = tmpccmr2;
00003e  8381              STRH     r1,[r0,#0x1c]
;;;3337     TIMx->CCER = tmpccer ;
000040  8402              STRH     r2,[r0,#0x20]
;;;3338   }
000042  bdf0              POP      {r4-r7,pc}
;;;3339   
                          ENDP


                          AREA ||i.TIM_ARRPreloadConfig||, CODE, READONLY, ALIGN=1

                  TIM_ARRPreloadConfig PROC
;;;515      */
;;;516    void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  b121              CBZ      r1,|L5.12|
;;;517    {
;;;518      /* Check the parameters */
;;;519      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;520      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;521    
;;;522      if (NewState != DISABLE)
;;;523      {
;;;524        /* Set the ARR Preload Bit */
;;;525        TIMx->CR1 |= TIM_CR1_ARPE;
000002  8802              LDRH     r2,[r0,#0]
000004  f0420280          ORR      r2,r2,#0x80
000008  8002              STRH     r2,[r0,#0]
00000a  e004              B        |L5.22|
                  |L5.12|
;;;526      }
;;;527      else
;;;528      {
;;;529        /* Reset the ARR Preload Bit */
;;;530        TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
00000c  8802              LDRH     r2,[r0,#0]
00000e  f64f737f          MOV      r3,#0xff7f
000012  401a              ANDS     r2,r2,r3
000014  8002              STRH     r2,[r0,#0]
                  |L5.22|
;;;531      }
;;;532    }
000016  4770              BX       lr
;;;533    
                          ENDP


                          AREA ||i.TIM_BDTRConfig||, CODE, READONLY, ALIGN=1

                  TIM_BDTRConfig PROC
;;;2210     */
;;;2211   void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
000000  880a              LDRH     r2,[r1,#0]
;;;2212   {
;;;2213     /* Check the parameters */
;;;2214     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;2215     assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
;;;2216     assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
;;;2217     assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
;;;2218     assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
;;;2219     assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
;;;2220     assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
;;;2221   
;;;2222     /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
;;;2223        the OSSI State, the dead time value and the Automatic Output Enable Bit */
;;;2224     TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
000002  884b              LDRH     r3,[r1,#2]
000004  431a              ORRS     r2,r2,r3
000006  888b              LDRH     r3,[r1,#4]
000008  431a              ORRS     r2,r2,r3
00000a  88cb              LDRH     r3,[r1,#6]
00000c  431a              ORRS     r2,r2,r3
00000e  890b              LDRH     r3,[r1,#8]
000010  431a              ORRS     r2,r2,r3
000012  894b              LDRH     r3,[r1,#0xa]
000014  431a              ORRS     r2,r2,r3
000016  898b              LDRH     r3,[r1,#0xc]
000018  431a              ORRS     r2,r2,r3
00001a  f8a02044          STRH     r2,[r0,#0x44]
;;;2225                TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
;;;2226                TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
;;;2227                TIM_BDTRInitStruct->TIM_AutomaticOutput;
;;;2228   }
00001e  4770              BX       lr
;;;2229   
                          ENDP


                          AREA ||i.TIM_BDTRStructInit||, CODE, READONLY, ALIGN=1

                  TIM_BDTRStructInit PROC
;;;2235     */
;;;2236   void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
000000  2100              MOVS     r1,#0
;;;2237   {
;;;2238     /* Set the default configuration */
;;;2239     TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
000002  8001              STRH     r1,[r0,#0]
;;;2240     TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
000004  8041              STRH     r1,[r0,#2]
;;;2241     TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
000006  8081              STRH     r1,[r0,#4]
;;;2242     TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
000008  80c1              STRH     r1,[r0,#6]
;;;2243     TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
00000a  8101              STRH     r1,[r0,#8]
;;;2244     TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
00000c  8141              STRH     r1,[r0,#0xa]
;;;2245     TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
00000e  8181              STRH     r1,[r0,#0xc]
;;;2246   }
000010  4770              BX       lr
;;;2247   
                          ENDP


                          AREA ||i.TIM_CCPreloadControl||, CODE, READONLY, ALIGN=1

                  TIM_CCPreloadControl PROC
;;;2304     */
;;;2305   void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  b121              CBZ      r1,|L8.12|
;;;2306   { 
;;;2307     /* Check the parameters */
;;;2308     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;2309     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2310     if (NewState != DISABLE)
;;;2311     {
;;;2312       /* Set the CCPC Bit */
;;;2313       TIMx->CR2 |= TIM_CR2_CCPC;
000002  8882              LDRH     r2,[r0,#4]
000004  f0420201          ORR      r2,r2,#1
000008  8082              STRH     r2,[r0,#4]
00000a  e004              B        |L8.22|
                  |L8.12|
;;;2314     }
;;;2315     else
;;;2316     {
;;;2317       /* Reset the CCPC Bit */
;;;2318       TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
00000c  8882              LDRH     r2,[r0,#4]
00000e  f64f73fe          MOV      r3,#0xfffe
000012  401a              ANDS     r2,r2,r3
000014  8082              STRH     r2,[r0,#4]
                  |L8.22|
;;;2319     }
;;;2320   }
000016  4770              BX       lr
;;;2321   /**
                          ENDP


                          AREA ||i.TIM_CCxCmd||, CODE, READONLY, ALIGN=1

                  TIM_CCxCmd PROC
;;;1777     */
;;;1778   void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
000000  b530              PUSH     {r4,r5,lr}
;;;1779   {
;;;1780     uint16_t tmp = 0;
000002  2300              MOVS     r3,#0
;;;1781   
;;;1782     /* Check the parameters */
;;;1783     assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
;;;1784     assert_param(IS_TIM_CHANNEL(TIM_Channel));
;;;1785     assert_param(IS_TIM_CCX(TIM_CCx));
;;;1786   
;;;1787     tmp = CCER_CCE_SET << TIM_Channel;
000004  2401              MOVS     r4,#1
000006  408c              LSLS     r4,r4,r1
000008  b2a3              UXTH     r3,r4
;;;1788   
;;;1789     /* Reset the CCxE Bit */
;;;1790     TIMx->CCER &= (uint16_t)~ tmp;
00000a  8c04              LDRH     r4,[r0,#0x20]
00000c  43dd              MVNS     r5,r3
00000e  b2ad              UXTH     r5,r5
000010  402c              ANDS     r4,r4,r5
000012  8404              STRH     r4,[r0,#0x20]
;;;1791   
;;;1792     /* Set or reset the CCxE Bit */ 
;;;1793     TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
000014  8c04              LDRH     r4,[r0,#0x20]
000016  fa02f501          LSL      r5,r2,r1
00001a  b2ad              UXTH     r5,r5
00001c  432c              ORRS     r4,r4,r5
00001e  8404              STRH     r4,[r0,#0x20]
;;;1794   }
000020  bd30              POP      {r4,r5,pc}
;;;1795   
                          ENDP


                          AREA ||i.TIM_CCxNCmd||, CODE, READONLY, ALIGN=1

                  TIM_CCxNCmd PROC
;;;1807     */
;;;1808   void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
000000  b530              PUSH     {r4,r5,lr}
;;;1809   {
;;;1810     uint16_t tmp = 0;
000002  2300              MOVS     r3,#0
;;;1811   
;;;1812     /* Check the parameters */
;;;1813     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;1814     assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
;;;1815     assert_param(IS_TIM_CCXN(TIM_CCxN));
;;;1816   
;;;1817     tmp = CCER_CCNE_SET << TIM_Channel;
000004  2404              MOVS     r4,#4
000006  408c              LSLS     r4,r4,r1
000008  b2a3              UXTH     r3,r4
;;;1818   
;;;1819     /* Reset the CCxNE Bit */
;;;1820     TIMx->CCER &= (uint16_t) ~tmp;
00000a  8c04              LDRH     r4,[r0,#0x20]
00000c  43dd              MVNS     r5,r3
00000e  b2ad              UXTH     r5,r5
000010  402c              ANDS     r4,r4,r5
000012  8404              STRH     r4,[r0,#0x20]
;;;1821   
;;;1822     /* Set or reset the CCxNE Bit */ 
;;;1823     TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
000014  8c04              LDRH     r4,[r0,#0x20]
000016  fa02f501          LSL      r5,r2,r1
00001a  b2ad              UXTH     r5,r5
00001c  432c              ORRS     r4,r4,r5
00001e  8404              STRH     r4,[r0,#0x20]
;;;1824   }
000020  bd30              POP      {r4,r5,pc}
;;;1825   /**
                          ENDP


                          AREA ||i.TIM_ClearFlag||, CODE, READONLY, ALIGN=1

                  TIM_ClearFlag PROC
;;;2474     */
;;;2475   void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
000000  43ca              MVNS     r2,r1
;;;2476   {  
;;;2477     /* Check the parameters */
;;;2478     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2479      
;;;2480     /* Clear the flags */
;;;2481     TIMx->SR = (uint16_t)~TIM_FLAG;
000002  8202              STRH     r2,[r0,#0x10]
;;;2482   }
000004  4770              BX       lr
;;;2483   
                          ENDP


                          AREA ||i.TIM_ClearITPendingBit||, CODE, READONLY, ALIGN=1

                  TIM_ClearITPendingBit PROC
;;;2543     */
;;;2544   void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
000000  43ca              MVNS     r2,r1
;;;2545   {
;;;2546     /* Check the parameters */
;;;2547     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2548   
;;;2549     /* Clear the IT pending Bit */
;;;2550     TIMx->SR = (uint16_t)~TIM_IT;
000002  8202              STRH     r2,[r0,#0x10]
;;;2551   }
000004  4770              BX       lr
;;;2552   
                          ENDP


                          AREA ||i.TIM_ClearOC1Ref||, CODE, READONLY, ALIGN=1

                  TIM_ClearOC1Ref PROC
;;;1467     */
;;;1468   void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000  460a              MOV      r2,r1
;;;1469   {
;;;1470     uint16_t tmpccmr1 = 0;
000002  2100              MOVS     r1,#0
;;;1471   
;;;1472     /* Check the parameters */
;;;1473     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1474     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1475   
;;;1476     tmpccmr1 = TIMx->CCMR1;
000004  8b01              LDRH     r1,[r0,#0x18]
;;;1477   
;;;1478     /* Reset the OC1CE Bit */
;;;1479     tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;
000006  f64f737f          MOV      r3,#0xff7f
00000a  4019              ANDS     r1,r1,r3
;;;1480   
;;;1481     /* Enable or Disable the Output Compare Clear Bit */
;;;1482     tmpccmr1 |= TIM_OCClear;
00000c  4311              ORRS     r1,r1,r2
;;;1483   
;;;1484     /* Write to TIMx CCMR1 register */
;;;1485     TIMx->CCMR1 = tmpccmr1;
00000e  8301              STRH     r1,[r0,#0x18]
;;;1486   }
000010  4770              BX       lr
;;;1487   
                          ENDP


                          AREA ||i.TIM_ClearOC2Ref||, CODE, READONLY, ALIGN=1

                  TIM_ClearOC2Ref PROC
;;;1497     */
;;;1498   void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000  460a              MOV      r2,r1
;;;1499   {
;;;1500     uint16_t tmpccmr1 = 0;
000002  2100              MOVS     r1,#0
;;;1501   
;;;1502     /* Check the parameters */
;;;1503     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1504     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1505   
;;;1506     tmpccmr1 = TIMx->CCMR1;
000004  8b01              LDRH     r1,[r0,#0x18]
;;;1507   
;;;1508     /* Reset the OC2CE Bit */
;;;1509     tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;
000006  f3c1010e          UBFX     r1,r1,#0,#15
;;;1510   
;;;1511     /* Enable or Disable the Output Compare Clear Bit */
;;;1512     tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
00000a  0613              LSLS     r3,r2,#24
00000c  ea414113          ORR      r1,r1,r3,LSR #16
;;;1513   
;;;1514     /* Write to TIMx CCMR1 register */
;;;1515     TIMx->CCMR1 = tmpccmr1;
000010  8301              STRH     r1,[r0,#0x18]
;;;1516   }
000012  4770              BX       lr
;;;1517   
                          ENDP


                          AREA ||i.TIM_ClearOC3Ref||, CODE, READONLY, ALIGN=1

                  TIM_ClearOC3Ref PROC
;;;1526     */
;;;1527   void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000  460a              MOV      r2,r1
;;;1528   {
;;;1529     uint16_t tmpccmr2 = 0;
000002  2100              MOVS     r1,#0
;;;1530   
;;;1531     /* Check the parameters */
;;;1532     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1533     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1534   
;;;1535     tmpccmr2 = TIMx->CCMR2;
000004  8b81              LDRH     r1,[r0,#0x1c]
;;;1536   
;;;1537     /* Reset the OC3CE Bit */
;;;1538     tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;
000006  f64f737f          MOV      r3,#0xff7f
00000a  4019              ANDS     r1,r1,r3
;;;1539   
;;;1540     /* Enable or Disable the Output Compare Clear Bit */
;;;1541     tmpccmr2 |= TIM_OCClear;
00000c  4311              ORRS     r1,r1,r2
;;;1542   
;;;1543     /* Write to TIMx CCMR2 register */
;;;1544     TIMx->CCMR2 = tmpccmr2;
00000e  8381              STRH     r1,[r0,#0x1c]
;;;1545   }
000010  4770              BX       lr
;;;1546   
                          ENDP


                          AREA ||i.TIM_ClearOC4Ref||, CODE, READONLY, ALIGN=1

                  TIM_ClearOC4Ref PROC
;;;1555     */
;;;1556   void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000  460a              MOV      r2,r1
;;;1557   {
;;;1558     uint16_t tmpccmr2 = 0;
000002  2100              MOVS     r1,#0
;;;1559   
;;;1560     /* Check the parameters */
;;;1561     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1562     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1563   
;;;1564     tmpccmr2 = TIMx->CCMR2;
000004  8b81              LDRH     r1,[r0,#0x1c]
;;;1565   
;;;1566     /* Reset the OC4CE Bit */
;;;1567     tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;
000006  f3c1010e          UBFX     r1,r1,#0,#15
;;;1568   
;;;1569     /* Enable or Disable the Output Compare Clear Bit */
;;;1570     tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
00000a  0613              LSLS     r3,r2,#24
00000c  ea414113          ORR      r1,r1,r3,LSR #16
;;;1571   
;;;1572     /* Write to TIMx CCMR2 register */
;;;1573     TIMx->CCMR2 = tmpccmr2;
000010  8381              STRH     r1,[r0,#0x1c]
;;;1574   }
000012  4770              BX       lr
;;;1575   
                          ENDP


                          AREA ||i.TIM_Cmd||, CODE, READONLY, ALIGN=1

                  TIM_Cmd PROC
;;;585      */
;;;586    void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  b121              CBZ      r1,|L17.12|
;;;587    {
;;;588      /* Check the parameters */
;;;589      assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
;;;590      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;591      
;;;592      if (NewState != DISABLE)
;;;593      {
;;;594        /* Enable the TIM Counter */
;;;595        TIMx->CR1 |= TIM_CR1_CEN;
000002  8802              LDRH     r2,[r0,#0]
000004  f0420201          ORR      r2,r2,#1
000008  8002              STRH     r2,[r0,#0]
00000a  e004              B        |L17.22|
                  |L17.12|
;;;596      }
;;;597      else
;;;598      {
;;;599        /* Disable the TIM Counter */
;;;600        TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
00000c  8802              LDRH     r2,[r0,#0]
00000e  f64f73fe          MOV      r3,#0xfffe
000012  401a              ANDS     r2,r2,r3
000014  8002              STRH     r2,[r0,#0]
                  |L17.22|
;;;601      }
;;;602    }
000016  4770              BX       lr
;;;603    /**
                          ENDP


                          AREA ||i.TIM_CounterModeConfig||, CODE, READONLY, ALIGN=1

                  TIM_CounterModeConfig PROC
;;;376      */
;;;377    void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
000000  460a              MOV      r2,r1
;;;378    {
;;;379      uint16_t tmpcr1 = 0;
000002  2100              MOVS     r1,#0
;;;380    
;;;381      /* Check the parameters */
;;;382      assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;383      assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
;;;384    
;;;385      tmpcr1 = TIMx->CR1;
000004  8801              LDRH     r1,[r0,#0]
;;;386    
;;;387      /* Reset the CMS and DIR Bits */
;;;388      tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
000006  f64f738f          MOV      r3,#0xff8f
00000a  4019              ANDS     r1,r1,r3
;;;389    
;;;390      /* Set the Counter Mode */
;;;391      tmpcr1 |= TIM_CounterMode;
00000c  4311              ORRS     r1,r1,r2
;;;392    
;;;393      /* Write to TIMx CR1 register */
;;;394      TIMx->CR1 = tmpcr1;
00000e  8001              STRH     r1,[r0,#0]
;;;395    }
000010  4770              BX       lr
;;;396    
                          ENDP


                          AREA ||i.TIM_CtrlPWMOutputs||, CODE, READONLY, ALIGN=1

                  TIM_CtrlPWMOutputs PROC
;;;2254     */
;;;2255   void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  b131              CBZ      r1,|L19.16|
;;;2256   {
;;;2257     /* Check the parameters */
;;;2258     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;2259     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2260   
;;;2261     if (NewState != DISABLE)
;;;2262     {
;;;2263       /* Enable the TIM Main Output */
;;;2264       TIMx->BDTR |= TIM_BDTR_MOE;
000002  f8b02044          LDRH     r2,[r0,#0x44]
000006  f4424200          ORR      r2,r2,#0x8000
00000a  f8a02044          STRH     r2,[r0,#0x44]
00000e  e005              B        |L19.28|
                  |L19.16|
;;;2265     }
;;;2266     else
;;;2267     {
;;;2268       /* Disable the TIM Main Output */
;;;2269       TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
000010  f8b02044          LDRH     r2,[r0,#0x44]
000014  f3c2020e          UBFX     r2,r2,#0,#15
000018  f8a02044          STRH     r2,[r0,#0x44]
                  |L19.28|
;;;2270     }  
;;;2271   }
00001c  4770              BX       lr
;;;2272   
                          ENDP


                          AREA ||i.TIM_DMACmd||, CODE, READONLY, ALIGN=1

                  TIM_DMACmd PROC
;;;2607     */
;;;2608   void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
000000  b510              PUSH     {r4,lr}
;;;2609   { 
;;;2610     /* Check the parameters */
;;;2611     assert_param(IS_TIM_LIST5_PERIPH(TIMx)); 
;;;2612     assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
;;;2613     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2614     
;;;2615     if (NewState != DISABLE)
000002  b11a              CBZ      r2,|L20.12|
;;;2616     {
;;;2617       /* Enable the DMA sources */
;;;2618       TIMx->DIER |= TIM_DMASource; 
000004  8983              LDRH     r3,[r0,#0xc]
000006  430b              ORRS     r3,r3,r1
000008  8183              STRH     r3,[r0,#0xc]
00000a  e004              B        |L20.22|
                  |L20.12|
;;;2619     }
;;;2620     else
;;;2621     {
;;;2622       /* Disable the DMA sources */
;;;2623       TIMx->DIER &= (uint16_t)~TIM_DMASource;
00000c  8983              LDRH     r3,[r0,#0xc]
00000e  43cc              MVNS     r4,r1
000010  b2a4              UXTH     r4,r4
000012  4023              ANDS     r3,r3,r4
000014  8183              STRH     r3,[r0,#0xc]
                  |L20.22|
;;;2624     }
;;;2625   }
000016  bd10              POP      {r4,pc}
;;;2626   
                          ENDP


                          AREA ||i.TIM_DMAConfig||, CODE, READONLY, ALIGN=1

                  TIM_DMAConfig PROC
;;;2580     */
;;;2581   void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
000000  ea410302          ORR      r3,r1,r2
;;;2582   {
;;;2583     /* Check the parameters */
;;;2584     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2585     assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); 
;;;2586     assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
;;;2587   
;;;2588     /* Set the DMA Base and the DMA Burst Length */
;;;2589     TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
000004  f8a03048          STRH     r3,[r0,#0x48]
;;;2590   }
000008  4770              BX       lr
;;;2591   
                          ENDP


                          AREA ||i.TIM_DeInit||, CODE, READONLY, ALIGN=2

                  TIM_DeInit PROC
;;;193      */
;;;194    void TIM_DeInit(TIM_TypeDef* TIMx)
000000  b510              PUSH     {r4,lr}
;;;195    {
000002  4604              MOV      r4,r0
;;;196      /* Check the parameters */
;;;197      assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
;;;198     
;;;199      if (TIMx == TIM1)
000004  4855              LDR      r0,|L22.348|
000006  4284              CMP      r4,r0
000008  d108              BNE      |L22.28|
;;;200      {
;;;201        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
00000a  2101              MOVS     r1,#1
00000c  4608              MOV      r0,r1
00000e  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;202        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
000012  2100              MOVS     r1,#0
000014  2001              MOVS     r0,#1
000016  f7fffffe          BL       RCC_APB2PeriphResetCmd
00001a  e09d              B        |L22.344|
                  |L22.28|
;;;203      } 
;;;204      else if (TIMx == TIM2) 
00001c  f1b44f80          CMP      r4,#0x40000000
000020  d108              BNE      |L22.52|
;;;205      {     
;;;206        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
000022  2101              MOVS     r1,#1
000024  4608              MOV      r0,r1
000026  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;207        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
00002a  2100              MOVS     r1,#0
00002c  2001              MOVS     r0,#1
00002e  f7fffffe          BL       RCC_APB1PeriphResetCmd
000032  e091              B        |L22.344|
                  |L22.52|
;;;208      }  
;;;209      else if (TIMx == TIM3)
000034  484a              LDR      r0,|L22.352|
000036  4284              CMP      r4,r0
000038  d108              BNE      |L22.76|
;;;210      { 
;;;211        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
00003a  2101              MOVS     r1,#1
00003c  2002              MOVS     r0,#2
00003e  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;212        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
000042  2100              MOVS     r1,#0
000044  2002              MOVS     r0,#2
000046  f7fffffe          BL       RCC_APB1PeriphResetCmd
00004a  e085              B        |L22.344|
                  |L22.76|
;;;213      }  
;;;214      else if (TIMx == TIM4)
00004c  4845              LDR      r0,|L22.356|
00004e  4284              CMP      r4,r0
000050  d108              BNE      |L22.100|
;;;215      { 
;;;216        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
000052  2101              MOVS     r1,#1
000054  2004              MOVS     r0,#4
000056  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;217        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
00005a  2100              MOVS     r1,#0
00005c  2004              MOVS     r0,#4
00005e  f7fffffe          BL       RCC_APB1PeriphResetCmd
000062  e079              B        |L22.344|
                  |L22.100|
;;;218      }  
;;;219      else if (TIMx == TIM5)
000064  4840              LDR      r0,|L22.360|
000066  4284              CMP      r4,r0
000068  d108              BNE      |L22.124|
;;;220      {      
;;;221        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
00006a  2101              MOVS     r1,#1
00006c  2008              MOVS     r0,#8
00006e  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;222        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
000072  2100              MOVS     r1,#0
000074  2008              MOVS     r0,#8
000076  f7fffffe          BL       RCC_APB1PeriphResetCmd
00007a  e06d              B        |L22.344|
                  |L22.124|
;;;223      }  
;;;224      else if (TIMx == TIM6)  
00007c  483b              LDR      r0,|L22.364|
00007e  4284              CMP      r4,r0
000080  d108              BNE      |L22.148|
;;;225      {    
;;;226        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
000082  2101              MOVS     r1,#1
000084  2010              MOVS     r0,#0x10
000086  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;227        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
00008a  2100              MOVS     r1,#0
00008c  2010              MOVS     r0,#0x10
00008e  f7fffffe          BL       RCC_APB1PeriphResetCmd
000092  e061              B        |L22.344|
                  |L22.148|
;;;228      }  
;;;229      else if (TIMx == TIM7)
000094  4836              LDR      r0,|L22.368|
000096  4284              CMP      r4,r0
000098  d108              BNE      |L22.172|
;;;230      {      
;;;231        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
00009a  2101              MOVS     r1,#1
00009c  2020              MOVS     r0,#0x20
00009e  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;232        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
0000a2  2100              MOVS     r1,#0
0000a4  2020              MOVS     r0,#0x20
0000a6  f7fffffe          BL       RCC_APB1PeriphResetCmd
0000aa  e055              B        |L22.344|
                  |L22.172|
;;;233      }  
;;;234      else if (TIMx == TIM8)
0000ac  4831              LDR      r0,|L22.372|
0000ae  4284              CMP      r4,r0
0000b0  d108              BNE      |L22.196|
;;;235      {      
;;;236        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
0000b2  2101              MOVS     r1,#1
0000b4  2002              MOVS     r0,#2
0000b6  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;237        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);  
0000ba  2100              MOVS     r1,#0
0000bc  2002              MOVS     r0,#2
0000be  f7fffffe          BL       RCC_APB2PeriphResetCmd
0000c2  e049              B        |L22.344|
                  |L22.196|
;;;238      }  
;;;239      else if (TIMx == TIM9)
0000c4  482c              LDR      r0,|L22.376|
0000c6  4284              CMP      r4,r0
0000c8  d109              BNE      |L22.222|
;;;240      {      
;;;241        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
0000ca  2101              MOVS     r1,#1
0000cc  0408              LSLS     r0,r1,#16
0000ce  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;242        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);  
0000d2  2100              MOVS     r1,#0
0000d4  f44f3080          MOV      r0,#0x10000
0000d8  f7fffffe          BL       RCC_APB2PeriphResetCmd
0000dc  e03c              B        |L22.344|
                  |L22.222|
;;;243       }  
;;;244      else if (TIMx == TIM10)
0000de  4827              LDR      r0,|L22.380|
0000e0  4284              CMP      r4,r0
0000e2  d109              BNE      |L22.248|
;;;245      {      
;;;246        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
0000e4  2101              MOVS     r1,#1
0000e6  0448              LSLS     r0,r1,#17
0000e8  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;247        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);  
0000ec  2100              MOVS     r1,#0
0000ee  f44f3000          MOV      r0,#0x20000
0000f2  f7fffffe          BL       RCC_APB2PeriphResetCmd
0000f6  e02f              B        |L22.344|
                  |L22.248|
;;;248      }  
;;;249      else if (TIMx == TIM11) 
0000f8  4821              LDR      r0,|L22.384|
0000fa  4284              CMP      r4,r0
0000fc  d109              BNE      |L22.274|
;;;250      {     
;;;251        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
0000fe  2101              MOVS     r1,#1
000100  0488              LSLS     r0,r1,#18
000102  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;252        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);  
000106  2100              MOVS     r1,#0
000108  f44f2080          MOV      r0,#0x40000
00010c  f7fffffe          BL       RCC_APB2PeriphResetCmd
000110  e022              B        |L22.344|
                  |L22.274|
;;;253      }  
;;;254      else if (TIMx == TIM12)
000112  481c              LDR      r0,|L22.388|
000114  4284              CMP      r4,r0
000116  d108              BNE      |L22.298|
;;;255      {      
;;;256        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
000118  2101              MOVS     r1,#1
00011a  2040              MOVS     r0,#0x40
00011c  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;257        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);  
000120  2100              MOVS     r1,#0
000122  2040              MOVS     r0,#0x40
000124  f7fffffe          BL       RCC_APB1PeriphResetCmd
000128  e016              B        |L22.344|
                  |L22.298|
;;;258      }  
;;;259      else if (TIMx == TIM13) 
00012a  4817              LDR      r0,|L22.392|
00012c  4284              CMP      r4,r0
00012e  d108              BNE      |L22.322|
;;;260      {       
;;;261        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
000130  2101              MOVS     r1,#1
000132  2080              MOVS     r0,#0x80
000134  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;262        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);  
000138  2100              MOVS     r1,#0
00013a  2080              MOVS     r0,#0x80
00013c  f7fffffe          BL       RCC_APB1PeriphResetCmd
000140  e00a              B        |L22.344|
                  |L22.322|
;;;263      }  
;;;264      else
;;;265      { 
;;;266        if (TIMx == TIM14) 
000142  4812              LDR      r0,|L22.396|
000144  4284              CMP      r4,r0
000146  d107              BNE      |L22.344|
;;;267        {     
;;;268          RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
000148  2101              MOVS     r1,#1
00014a  1580              ASRS     r0,r0,#22
00014c  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;269          RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); 
000150  2100              MOVS     r1,#0
000152  15a0              ASRS     r0,r4,#22
000154  f7fffffe          BL       RCC_APB1PeriphResetCmd
                  |L22.344|
;;;270        }   
;;;271      }
;;;272    }
000158  bd10              POP      {r4,pc}
;;;273    
                          ENDP

00015a  0000              DCW      0x0000
                  |L22.348|
                          DCD      0x40010000
                  |L22.352|
                          DCD      0x40000400
                  |L22.356|
                          DCD      0x40000800
                  |L22.360|
                          DCD      0x40000c00
                  |L22.364|
                          DCD      0x40001000
                  |L22.368|
                          DCD      0x40001400
                  |L22.372|
                          DCD      0x40010400
                  |L22.376|
                          DCD      0x40014000
                  |L22.380|
                          DCD      0x40014400
                  |L22.384|
                          DCD      0x40014800
                  |L22.388|
                          DCD      0x40001800
                  |L22.392|
                          DCD      0x40001c00
                  |L22.396|
                          DCD      0x40002000

                          AREA ||i.TIM_ETRClockMode1Config||, CODE, READONLY, ALIGN=1

                  TIM_ETRClockMode1Config PROC
;;;2763     */
;;;2764   void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
000000  e92d41f0          PUSH     {r4-r8,lr}
;;;2765                               uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
;;;2766   {
000004  4605              MOV      r5,r0
000006  460e              MOV      r6,r1
000008  4617              MOV      r7,r2
00000a  4698              MOV      r8,r3
;;;2767     uint16_t tmpsmcr = 0;
00000c  2400              MOVS     r4,#0
;;;2768   
;;;2769     /* Check the parameters */
;;;2770     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2771     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;2772     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;2773     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;2774     /* Configure the ETR Clock source */
;;;2775     TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
00000e  4643              MOV      r3,r8
000010  463a              MOV      r2,r7
000012  4631              MOV      r1,r6
000014  4628              MOV      r0,r5
000016  f7fffffe          BL       TIM_ETRConfig
;;;2776     
;;;2777     /* Get the TIMx SMCR register value */
;;;2778     tmpsmcr = TIMx->SMCR;
00001a  892c              LDRH     r4,[r5,#8]
;;;2779   
;;;2780     /* Reset the SMS Bits */
;;;2781     tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
00001c  f64f70f8          MOV      r0,#0xfff8
000020  4004              ANDS     r4,r4,r0
;;;2782   
;;;2783     /* Select the External clock mode1 */
;;;2784     tmpsmcr |= TIM_SlaveMode_External1;
000022  f0440407          ORR      r4,r4,#7
;;;2785   
;;;2786     /* Select the Trigger selection : ETRF */
;;;2787     tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
000026  f64f708f          MOV      r0,#0xff8f
00002a  4004              ANDS     r4,r4,r0
;;;2788     tmpsmcr |= TIM_TS_ETRF;
00002c  f0440470          ORR      r4,r4,#0x70
;;;2789   
;;;2790     /* Write to TIMx SMCR */
;;;2791     TIMx->SMCR = tmpsmcr;
000030  812c              STRH     r4,[r5,#8]
;;;2792   }
000032  e8bd81f0          POP      {r4-r8,pc}
;;;2793   
                          ENDP


                          AREA ||i.TIM_ETRClockMode2Config||, CODE, READONLY, ALIGN=1

                  TIM_ETRClockMode2Config PROC
;;;2810     */
;;;2811   void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
000000  b5f0              PUSH     {r4-r7,lr}
;;;2812                                uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
;;;2813   {
000002  4604              MOV      r4,r0
000004  460d              MOV      r5,r1
000006  4616              MOV      r6,r2
000008  461f              MOV      r7,r3
;;;2814     /* Check the parameters */
;;;2815     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2816     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;2817     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;2818     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;2819   
;;;2820     /* Configure the ETR Clock source */
;;;2821     TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
00000a  463b              MOV      r3,r7
00000c  4632              MOV      r2,r6
00000e  4629              MOV      r1,r5
000010  4620              MOV      r0,r4
000012  f7fffffe          BL       TIM_ETRConfig
;;;2822   
;;;2823     /* Enable the External clock mode2 */
;;;2824     TIMx->SMCR |= TIM_SMCR_ECE;
000016  8920              LDRH     r0,[r4,#8]
000018  f4404080          ORR      r0,r0,#0x4000
00001c  8120              STRH     r0,[r4,#8]
;;;2825   }
00001e  bdf0              POP      {r4-r7,pc}
;;;2826   /**
                          ENDP


                          AREA ||i.TIM_ETRConfig||, CODE, READONLY, ALIGN=1

                  TIM_ETRConfig PROC
;;;2998     */
;;;2999   void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
000000  b510              PUSH     {r4,lr}
;;;3000                      uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
;;;3001   {
000002  468c              MOV      r12,r1
;;;3002     uint16_t tmpsmcr = 0;
000004  2100              MOVS     r1,#0
;;;3003   
;;;3004     /* Check the parameters */
;;;3005     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;3006     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;3007     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;3008     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;3009   
;;;3010     tmpsmcr = TIMx->SMCR;
000006  8901              LDRH     r1,[r0,#8]
;;;3011   
;;;3012     /* Reset the ETR Bits */
;;;3013     tmpsmcr &= SMCR_ETR_MASK;
000008  b2c9              UXTB     r1,r1
;;;3014   
;;;3015     /* Set the Prescaler, the Filter value and the Polarity */
;;;3016     tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
00000a  061c              LSLS     r4,r3,#24
00000c  ea424414          ORR      r4,r2,r4,LSR #16
000010  ea44040c          ORR      r4,r4,r12
000014  4321              ORRS     r1,r1,r4
;;;3017   
;;;3018     /* Write to TIMx SMCR */
;;;3019     TIMx->SMCR = tmpsmcr;
000016  8101              STRH     r1,[r0,#8]
;;;3020   }
000018  bd10              POP      {r4,pc}
;;;3021   /**
                          ENDP


                          AREA ||i.TIM_EncoderInterfaceConfig||, CODE, READONLY, ALIGN=1

                  TIM_EncoderInterfaceConfig PROC
;;;3056     */
;;;3057   void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
000000  b570              PUSH     {r4-r6,lr}
;;;3058                                   uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
;;;3059   {
000002  468c              MOV      r12,r1
000004  4614              MOV      r4,r2
000006  461d              MOV      r5,r3
;;;3060     uint16_t tmpsmcr = 0;
000008  2100              MOVS     r1,#0
;;;3061     uint16_t tmpccmr1 = 0;
00000a  2200              MOVS     r2,#0
;;;3062     uint16_t tmpccer = 0;
00000c  2300              MOVS     r3,#0
;;;3063       
;;;3064     /* Check the parameters */
;;;3065     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;3066     assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
;;;3067     assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
;;;3068     assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
;;;3069   
;;;3070     /* Get the TIMx SMCR register value */
;;;3071     tmpsmcr = TIMx->SMCR;
00000e  8901              LDRH     r1,[r0,#8]
;;;3072   
;;;3073     /* Get the TIMx CCMR1 register value */
;;;3074     tmpccmr1 = TIMx->CCMR1;
000010  8b02              LDRH     r2,[r0,#0x18]
;;;3075   
;;;3076     /* Get the TIMx CCER register value */
;;;3077     tmpccer = TIMx->CCER;
000012  8c03              LDRH     r3,[r0,#0x20]
;;;3078   
;;;3079     /* Set the encoder Mode */
;;;3080     tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
000014  f64f76f8          MOV      r6,#0xfff8
000018  4031              ANDS     r1,r1,r6
;;;3081     tmpsmcr |= TIM_EncoderMode;
00001a  ea41010c          ORR      r1,r1,r12
;;;3082   
;;;3083     /* Select the Capture Compare 1 and the Capture Compare 2 as input */
;;;3084     tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
00001e  f64f46fc          MOV      r6,#0xfcfc
000022  4032              ANDS     r2,r2,r6
;;;3085     tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
000024  f2401601          MOV      r6,#0x101
000028  4332              ORRS     r2,r2,r6
;;;3086   
;;;3087     /* Set the TI1 and the TI2 Polarities */
;;;3088     tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
00002a  f64f76dd          MOV      r6,#0xffdd
00002e  4033              ANDS     r3,r3,r6
;;;3089     tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
000030  052e              LSLS     r6,r5,#20
000032  ea444616          ORR      r6,r4,r6,LSR #16
000036  4333              ORRS     r3,r3,r6
;;;3090   
;;;3091     /* Write to TIMx SMCR */
;;;3092     TIMx->SMCR = tmpsmcr;
000038  8101              STRH     r1,[r0,#8]
;;;3093   
;;;3094     /* Write to TIMx CCMR1 */
;;;3095     TIMx->CCMR1 = tmpccmr1;
00003a  8302              STRH     r2,[r0,#0x18]
;;;3096   
;;;3097     /* Write to TIMx CCER */
;;;3098     TIMx->CCER = tmpccer;
00003c  8403              STRH     r3,[r0,#0x20]
;;;3099   }
00003e  bd70              POP      {r4-r6,pc}
;;;3100   
                          ENDP


                          AREA ||i.TIM_ForcedOC1Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC1Config PROC
;;;1115     */
;;;1116   void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  460a              MOV      r2,r1
;;;1117   {
;;;1118     uint16_t tmpccmr1 = 0;
000002  2100              MOVS     r1,#0
;;;1119   
;;;1120     /* Check the parameters */
;;;1121     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1122     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1123     tmpccmr1 = TIMx->CCMR1;
000004  8b01              LDRH     r1,[r0,#0x18]
;;;1124   
;;;1125     /* Reset the OC1M Bits */
;;;1126     tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;
000006  f64f738f          MOV      r3,#0xff8f
00000a  4019              ANDS     r1,r1,r3
;;;1127   
;;;1128     /* Configure The Forced output Mode */
;;;1129     tmpccmr1 |= TIM_ForcedAction;
00000c  4311              ORRS     r1,r1,r2
;;;1130   
;;;1131     /* Write to TIMx CCMR1 register */
;;;1132     TIMx->CCMR1 = tmpccmr1;
00000e  8301              STRH     r1,[r0,#0x18]
;;;1133   }
000010  4770              BX       lr
;;;1134   
                          ENDP


                          AREA ||i.TIM_ForcedOC2Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC2Config PROC
;;;1144     */
;;;1145   void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  460a              MOV      r2,r1
;;;1146   {
;;;1147     uint16_t tmpccmr1 = 0;
000002  2100              MOVS     r1,#0
;;;1148   
;;;1149     /* Check the parameters */
;;;1150     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1151     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1152     tmpccmr1 = TIMx->CCMR1;
000004  8b01              LDRH     r1,[r0,#0x18]
;;;1153   
;;;1154     /* Reset the OC2M Bits */
;;;1155     tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;
000006  f64873ff          MOV      r3,#0x8fff
00000a  4019              ANDS     r1,r1,r3
;;;1156   
;;;1157     /* Configure The Forced output Mode */
;;;1158     tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
00000c  0613              LSLS     r3,r2,#24
00000e  ea414113          ORR      r1,r1,r3,LSR #16
;;;1159   
;;;1160     /* Write to TIMx CCMR1 register */
;;;1161     TIMx->CCMR1 = tmpccmr1;
000012  8301              STRH     r1,[r0,#0x18]
;;;1162   }
000014  4770              BX       lr
;;;1163   
                          ENDP


                          AREA ||i.TIM_ForcedOC3Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC3Config PROC
;;;1172     */
;;;1173   void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  460a              MOV      r2,r1
;;;1174   {
;;;1175     uint16_t tmpccmr2 = 0;
000002  2100              MOVS     r1,#0
;;;1176   
;;;1177     /* Check the parameters */
;;;1178     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1179     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1180   
;;;1181     tmpccmr2 = TIMx->CCMR2;
000004  8b81              LDRH     r1,[r0,#0x1c]
;;;1182   
;;;1183     /* Reset the OC1M Bits */
;;;1184     tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;
000006  f64f738f          MOV      r3,#0xff8f
00000a  4019              ANDS     r1,r1,r3
;;;1185   
;;;1186     /* Configure The Forced output Mode */
;;;1187     tmpccmr2 |= TIM_ForcedAction;
00000c  4311              ORRS     r1,r1,r2
;;;1188   
;;;1189     /* Write to TIMx CCMR2 register */
;;;1190     TIMx->CCMR2 = tmpccmr2;
00000e  8381              STRH     r1,[r0,#0x1c]
;;;1191   }
000010  4770              BX       lr
;;;1192   
                          ENDP


                          AREA ||i.TIM_ForcedOC4Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC4Config PROC
;;;1201     */
;;;1202   void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  460a              MOV      r2,r1
;;;1203   {
;;;1204     uint16_t tmpccmr2 = 0;
000002  2100              MOVS     r1,#0
;;;1205   
;;;1206     /* Check the parameters */
;;;1207     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1208     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1209     tmpccmr2 = TIMx->CCMR2;
000004  8b81              LDRH     r1,[r0,#0x1c]
;;;1210   
;;;1211     /* Reset the OC2M Bits */
;;;1212     tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;
000006  f64873ff          MOV      r3,#0x8fff
00000a  4019              ANDS     r1,r1,r3
;;;1213   
;;;1214     /* Configure The Forced output Mode */
;;;1215     tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
00000c  0613              LSLS     r3,r2,#24
00000e  ea414113          ORR      r1,r1,r3,LSR #16
;;;1216   
;;;1217     /* Write to TIMx CCMR2 register */
;;;1218     TIMx->CCMR2 = tmpccmr2;
000012  8381              STRH     r1,[r0,#0x1c]
;;;1219   }
000014  4770              BX       lr
;;;1220   
                          ENDP


                          AREA ||i.TIM_GenerateEvent||, CODE, READONLY, ALIGN=1

                  TIM_GenerateEvent PROC
;;;2399     */
;;;2400   void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
000000  8281              STRH     r1,[r0,#0x14]
;;;2401   { 
;;;2402     /* Check the parameters */
;;;2403     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2404     assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
;;;2405    
;;;2406     /* Set the event sources */
;;;2407     TIMx->EGR = TIM_EventSource;
;;;2408   }
000002  4770              BX       lr
;;;2409   
                          ENDP


                          AREA ||i.TIM_GetCapture1||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture1 PROC
;;;2021     */
;;;2022   uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
000000  4601              MOV      r1,r0
;;;2023   {
;;;2024     /* Check the parameters */
;;;2025     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;2026   
;;;2027     /* Get the Capture 1 Register value */
;;;2028     return TIMx->CCR1;
000002  6b48              LDR      r0,[r1,#0x34]
;;;2029   }
000004  4770              BX       lr
;;;2030   
                          ENDP


                          AREA ||i.TIM_GetCapture2||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture2 PROC
;;;2036     */
;;;2037   uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
000000  4601              MOV      r1,r0
;;;2038   {
;;;2039     /* Check the parameters */
;;;2040     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2041   
;;;2042     /* Get the Capture 2 Register value */
;;;2043     return TIMx->CCR2;
000002  6b88              LDR      r0,[r1,#0x38]
;;;2044   }
000004  4770              BX       lr
;;;2045   
                          ENDP


                          AREA ||i.TIM_GetCapture3||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture3 PROC
;;;2050     */
;;;2051   uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
000000  4601              MOV      r1,r0
;;;2052   {
;;;2053     /* Check the parameters */
;;;2054     assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
;;;2055   
;;;2056     /* Get the Capture 3 Register value */
;;;2057     return TIMx->CCR3;
000002  6bc8              LDR      r0,[r1,#0x3c]
;;;2058   }
000004  4770              BX       lr
;;;2059   
                          ENDP


                          AREA ||i.TIM_GetCapture4||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture4 PROC
;;;2064     */
;;;2065   uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
000000  4601              MOV      r1,r0
;;;2066   {
;;;2067     /* Check the parameters */
;;;2068     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2069   
;;;2070     /* Get the Capture 4 Register value */
;;;2071     return TIMx->CCR4;
000002  6c08              LDR      r0,[r1,#0x40]
;;;2072   }
000004  4770              BX       lr
;;;2073   
                          ENDP


                          AREA ||i.TIM_GetCounter||, CODE, READONLY, ALIGN=1

                  TIM_GetCounter PROC
;;;431      */
;;;432    uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
000000  4601              MOV      r1,r0
;;;433    {
;;;434      /* Check the parameters */
;;;435      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;436    
;;;437      /* Get the Counter Register value */
;;;438      return TIMx->CNT;
000002  6a48              LDR      r0,[r1,#0x24]
;;;439    }
000004  4770              BX       lr
;;;440    
                          ENDP


                          AREA ||i.TIM_GetFlagStatus||, CODE, READONLY, ALIGN=1

                  TIM_GetFlagStatus PROC
;;;2432     */
;;;2433   FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
000000  4602              MOV      r2,r0
;;;2434   { 
;;;2435     ITStatus bitstatus = RESET;  
000002  2000              MOVS     r0,#0
;;;2436     /* Check the parameters */
;;;2437     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2438     assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
;;;2439   
;;;2440     
;;;2441     if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
000004  8a13              LDRH     r3,[r2,#0x10]
000006  420b              TST      r3,r1
000008  d001              BEQ      |L37.14|
;;;2442     {
;;;2443       bitstatus = SET;
00000a  2001              MOVS     r0,#1
00000c  e000              B        |L37.16|
                  |L37.14|
;;;2444     }
;;;2445     else
;;;2446     {
;;;2447       bitstatus = RESET;
00000e  2000              MOVS     r0,#0
                  |L37.16|
;;;2448     }
;;;2449     return bitstatus;
;;;2450   }
000010  4770              BX       lr
;;;2451   
                          ENDP


                          AREA ||i.TIM_GetITStatus||, CODE, READONLY, ALIGN=1

                  TIM_GetITStatus PROC
;;;2502     */
;;;2503   ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
000000  b510              PUSH     {r4,lr}
;;;2504   {
000002  4602              MOV      r2,r0
;;;2505     ITStatus bitstatus = RESET;  
000004  2000              MOVS     r0,#0
;;;2506     uint16_t itstatus = 0x0, itenable = 0x0;
000006  2300              MOVS     r3,#0
000008  4684              MOV      r12,r0
;;;2507     /* Check the parameters */
;;;2508     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2509     assert_param(IS_TIM_GET_IT(TIM_IT));
;;;2510      
;;;2511     itstatus = TIMx->SR & TIM_IT;
00000a  8a14              LDRH     r4,[r2,#0x10]
00000c  ea040301          AND      r3,r4,r1
;;;2512     
;;;2513     itenable = TIMx->DIER & TIM_IT;
000010  8994              LDRH     r4,[r2,#0xc]
000012  ea040c01          AND      r12,r4,r1
;;;2514     if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
000016  b123              CBZ      r3,|L38.34|
000018  f1bc0f00          CMP      r12,#0
00001c  d001              BEQ      |L38.34|
;;;2515     {
;;;2516       bitstatus = SET;
00001e  2001              MOVS     r0,#1
000020  e000              B        |L38.36|
                  |L38.34|
;;;2517     }
;;;2518     else
;;;2519     {
;;;2520       bitstatus = RESET;
000022  2000              MOVS     r0,#0
                  |L38.36|
;;;2521     }
;;;2522     return bitstatus;
;;;2523   }
000024  bd10              POP      {r4,pc}
;;;2524   
                          ENDP


                          AREA ||i.TIM_GetPrescaler||, CODE, READONLY, ALIGN=1

                  TIM_GetPrescaler PROC
;;;445      */
;;;446    uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
000000  4601              MOV      r1,r0
;;;447    {
;;;448      /* Check the parameters */
;;;449      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;450    
;;;451      /* Get the Prescaler Register value */
;;;452      return TIMx->PSC;
000002  8d08              LDRH     r0,[r1,#0x28]
;;;453    }
000004  4770              BX       lr
;;;454    
                          ENDP


                          AREA ||i.TIM_ICInit||, CODE, READONLY, ALIGN=1

                  TIM_ICInit PROC
;;;1889     */
;;;1890   void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
000000  b570              PUSH     {r4-r6,lr}
;;;1891   {
000002  4605              MOV      r5,r0
000004  460c              MOV      r4,r1
;;;1892     /* Check the parameters */
;;;1893     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1894     assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
;;;1895     assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
;;;1896     assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
;;;1897     assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
;;;1898     
;;;1899     if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
000006  8820              LDRH     r0,[r4,#0]
000008  b950              CBNZ     r0,|L40.32|
;;;1900     {
;;;1901       /* TI1 Configuration */
;;;1902       TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
00000a  8923              LDRH     r3,[r4,#8]
00000c  88a2              LDRH     r2,[r4,#4]
00000e  8861              LDRH     r1,[r4,#2]
000010  4628              MOV      r0,r5
000012  f7fffffe          BL       TI1_Config
;;;1903                  TIM_ICInitStruct->TIM_ICSelection,
;;;1904                  TIM_ICInitStruct->TIM_ICFilter);
;;;1905       /* Set the Input Capture Prescaler value */
;;;1906       TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000016  88e1              LDRH     r1,[r4,#6]
000018  4628              MOV      r0,r5
00001a  f7fffffe          BL       TIM_SetIC1Prescaler
00001e  e025              B        |L40.108|
                  |L40.32|
;;;1907     }
;;;1908     else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
000020  8820              LDRH     r0,[r4,#0]
000022  2804              CMP      r0,#4
000024  d10a              BNE      |L40.60|
;;;1909     {
;;;1910       /* TI2 Configuration */
;;;1911       assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1912       TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
000026  8923              LDRH     r3,[r4,#8]
000028  88a2              LDRH     r2,[r4,#4]
00002a  8861              LDRH     r1,[r4,#2]
00002c  4628              MOV      r0,r5
00002e  f7fffffe          BL       TI2_Config
;;;1913                  TIM_ICInitStruct->TIM_ICSelection,
;;;1914                  TIM_ICInitStruct->TIM_ICFilter);
;;;1915       /* Set the Input Capture Prescaler value */
;;;1916       TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000032  88e1              LDRH     r1,[r4,#6]
000034  4628              MOV      r0,r5
000036  f7fffffe          BL       TIM_SetIC2Prescaler
00003a  e017              B        |L40.108|
                  |L40.60|
;;;1917     }
;;;1918     else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
00003c  8820              LDRH     r0,[r4,#0]
00003e  2808              CMP      r0,#8
000040  d10a              BNE      |L40.88|
;;;1919     {
;;;1920       /* TI3 Configuration */
;;;1921       assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1922       TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
000042  8923              LDRH     r3,[r4,#8]
000044  88a2              LDRH     r2,[r4,#4]
000046  8861              LDRH     r1,[r4,#2]
000048  4628              MOV      r0,r5
00004a  f7fffffe          BL       TI3_Config
;;;1923                  TIM_ICInitStruct->TIM_ICSelection,
;;;1924                  TIM_ICInitStruct->TIM_ICFilter);
;;;1925       /* Set the Input Capture Prescaler value */
;;;1926       TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00004e  88e1              LDRH     r1,[r4,#6]
000050  4628              MOV      r0,r5
000052  f7fffffe          BL       TIM_SetIC3Prescaler
000056  e009              B        |L40.108|
                  |L40.88|
;;;1927     }
;;;1928     else
;;;1929     {
;;;1930       /* TI4 Configuration */
;;;1931       assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1932       TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
000058  8923              LDRH     r3,[r4,#8]
00005a  88a2              LDRH     r2,[r4,#4]
00005c  8861              LDRH     r1,[r4,#2]
00005e  4628              MOV      r0,r5
000060  f7fffffe          BL       TI4_Config
;;;1933                  TIM_ICInitStruct->TIM_ICSelection,
;;;1934                  TIM_ICInitStruct->TIM_ICFilter);
;;;1935       /* Set the Input Capture Prescaler value */
;;;1936       TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000064  88e1              LDRH     r1,[r4,#6]
000066  4628              MOV      r0,r5
000068  f7fffffe          BL       TIM_SetIC4Prescaler
                  |L40.108|
;;;1937     }
;;;1938   }
00006c  bd70              POP      {r4-r6,pc}
;;;1939   
                          ENDP


                          AREA ||i.TIM_ICStructInit||, CODE, READONLY, ALIGN=1

                  TIM_ICStructInit PROC
;;;1945     */
;;;1946   void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
000000  2100              MOVS     r1,#0
;;;1947   {
;;;1948     /* Set the default configuration */
;;;1949     TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
000002  8001              STRH     r1,[r0,#0]
;;;1950     TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
000004  8041              STRH     r1,[r0,#2]
;;;1951     TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
000006  2101              MOVS     r1,#1
000008  8081              STRH     r1,[r0,#4]
;;;1952     TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
00000a  2100              MOVS     r1,#0
00000c  80c1              STRH     r1,[r0,#6]
;;;1953     TIM_ICInitStruct->TIM_ICFilter = 0x00;
00000e  8101              STRH     r1,[r0,#8]
;;;1954   }
000010  4770              BX       lr
;;;1955   
                          ENDP


                          AREA ||i.TIM_ITConfig||, CODE, READONLY, ALIGN=1

                  TIM_ITConfig PROC
;;;2361     */
;;;2362   void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
000000  b510              PUSH     {r4,lr}
;;;2363   {  
;;;2364     /* Check the parameters */
;;;2365     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2366     assert_param(IS_TIM_IT(TIM_IT));
;;;2367     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2368     
;;;2369     if (NewState != DISABLE)
000002  b11a              CBZ      r2,|L42.12|
;;;2370     {
;;;2371       /* Enable the Interrupt sources */
;;;2372       TIMx->DIER |= TIM_IT;
000004  8983              LDRH     r3,[r0,#0xc]
000006  430b              ORRS     r3,r3,r1
000008  8183              STRH     r3,[r0,#0xc]
00000a  e004              B        |L42.22|
                  |L42.12|
;;;2373     }
;;;2374     else
;;;2375     {
;;;2376       /* Disable the Interrupt sources */
;;;2377       TIMx->DIER &= (uint16_t)~TIM_IT;
00000c  8983              LDRH     r3,[r0,#0xc]
00000e  43cc              MVNS     r4,r1
000010  b2a4              UXTH     r4,r4
000012  4023              ANDS     r3,r3,r4
000014  8183              STRH     r3,[r0,#0xc]
                  |L42.22|
;;;2378     }
;;;2379   }
000016  bd10              POP      {r4,pc}
;;;2380   
                          ENDP


                          AREA ||i.TIM_ITRxExternalClockConfig||, CODE, READONLY, ALIGN=1

                  TIM_ITRxExternalClockConfig PROC
;;;2693     */
;;;2694   void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
000000  b530              PUSH     {r4,r5,lr}
;;;2695   {
000002  4604              MOV      r4,r0
000004  460d              MOV      r5,r1
;;;2696     /* Check the parameters */
;;;2697     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2698     assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
;;;2699   
;;;2700     /* Select the Internal Trigger */
;;;2701     TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
000006  4629              MOV      r1,r5
000008  4620              MOV      r0,r4
00000a  f7fffffe          BL       TIM_SelectInputTrigger
;;;2702   
;;;2703     /* Select the External clock mode1 */
;;;2704     TIMx->SMCR |= TIM_SlaveMode_External1;
00000e  8920              LDRH     r0,[r4,#8]
000010  f0400007          ORR      r0,r0,#7
000014  8120              STRH     r0,[r4,#8]
;;;2705   }
000016  bd30              POP      {r4,r5,pc}
;;;2706   
                          ENDP


                          AREA ||i.TIM_InternalClockConfig||, CODE, READONLY, ALIGN=1

                  TIM_InternalClockConfig PROC
;;;2672     */
;;;2673   void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
000000  8901              LDRH     r1,[r0,#8]
;;;2674   {
;;;2675     /* Check the parameters */
;;;2676     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2677   
;;;2678     /* Disable slave mode to clock the prescaler directly with the internal clock */
;;;2679     TIMx->SMCR &=  (uint16_t)~TIM_SMCR_SMS;
000002  f64f72f8          MOV      r2,#0xfff8
000006  4011              ANDS     r1,r1,r2
000008  8101              STRH     r1,[r0,#8]
;;;2680   }
00000a  4770              BX       lr
;;;2681   
                          ENDP


                          AREA ||i.TIM_OC1FastConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC1FastConfig PROC
;;;1346     */
;;;1347   void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000000  460a              MOV      r2,r1
;;;1348   {
;;;1349     uint16_t tmpccmr1 = 0;
000002  2100              MOVS     r1,#0
;;;1350   
;;;1351     /* Check the parameters */
;;;1352     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1353     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1354   
;;;1355     /* Get the TIMx CCMR1 register value */
;;;1356     tmpccmr1 = TIMx->CCMR1;
000004  8b01              LDRH     r1,[r0,#0x18]
;;;1357   
;;;1358     /* Reset the OC1FE Bit */
;;;1359     tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;
000006  f64f73fb          MOV      r3,#0xfffb
00000a  4019              ANDS     r1,r1,r3
;;;1360   
;;;1361     /* Enable or Disable the Output Compare Fast Bit */
;;;1362     tmpccmr1 |= TIM_OCFast;
00000c  4311              ORRS     r1,r1,r2
;;;1363   
;;;1364     /* Write to TIMx CCMR1 */
;;;1365     TIMx->CCMR1 = tmpccmr1;
00000e  8301              STRH     r1,[r0,#0x18]
;;;1366   }
000010  4770              BX       lr
;;;1367   
                          ENDP


                          AREA ||i.TIM_OC1Init||, CODE, READONLY, ALIGN=2

                  TIM_OC1Init PROC
;;;664      */
;;;665    void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;666    {
;;;667      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
000002  f04f0c00          MOV      r12,#0
000006  2200              MOVS     r2,#0
000008  2300              MOVS     r3,#0
;;;668       
;;;669      /* Check the parameters */
;;;670      assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
;;;671      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;672      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;673      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;674    
;;;675      /* Disable the Channel 1: Reset the CC1E Bit */
;;;676      TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
00000a  8c04              LDRH     r4,[r0,#0x20]
00000c  f64f75fe          MOV      r5,#0xfffe
000010  402c              ANDS     r4,r4,r5
000012  8404              STRH     r4,[r0,#0x20]
;;;677      
;;;678      /* Get the TIMx CCER register value */
;;;679      tmpccer = TIMx->CCER;
000014  8c02              LDRH     r2,[r0,#0x20]
;;;680      /* Get the TIMx CR2 register value */
;;;681      tmpcr2 =  TIMx->CR2;
000016  8883              LDRH     r3,[r0,#4]
;;;682      
;;;683      /* Get the TIMx CCMR1 register value */
;;;684      tmpccmrx = TIMx->CCMR1;
000018  f8b0c018          LDRH     r12,[r0,#0x18]
;;;685        
;;;686      /* Reset the Output Compare Mode Bits */
;;;687      tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;
00001c  f64f748f          MOV      r4,#0xff8f
000020  ea0c0c04          AND      r12,r12,r4
;;;688      tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;
000024  1eac              SUBS     r4,r5,#2
000026  ea0c0c04          AND      r12,r12,r4
;;;689      /* Select the Output Compare Mode */
;;;690      tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00002a  880c              LDRH     r4,[r1,#0]
00002c  ea440c0c          ORR      r12,r4,r12
;;;691      
;;;692      /* Reset the Output Polarity level */
;;;693      tmpccer &= (uint16_t)~TIM_CCER_CC1P;
000030  1e6c              SUBS     r4,r5,#1
000032  4022              ANDS     r2,r2,r4
;;;694      /* Set the Output Compare Polarity */
;;;695      tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
000034  898c              LDRH     r4,[r1,#0xc]
000036  4322              ORRS     r2,r2,r4
;;;696      
;;;697      /* Set the Output State */
;;;698      tmpccer |= TIM_OCInitStruct->TIM_OutputState;
000038  884c              LDRH     r4,[r1,#2]
00003a  4322              ORRS     r2,r2,r4
;;;699        
;;;700      if((TIMx == TIM1) || (TIMx == TIM8))
00003c  4c10              LDR      r4,|L46.128|
00003e  42a0              CMP      r0,r4
000040  d002              BEQ      |L46.72|
000042  4c10              LDR      r4,|L46.132|
000044  42a0              CMP      r0,r4
000046  d113              BNE      |L46.112|
                  |L46.72|
;;;701      {
;;;702        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;703        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;704        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;705        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;706        
;;;707        /* Reset the Output N Polarity level */
;;;708        tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
000048  f64f74f7          MOV      r4,#0xfff7
00004c  4022              ANDS     r2,r2,r4
;;;709        /* Set the Output N Polarity */
;;;710        tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
00004e  89cc              LDRH     r4,[r1,#0xe]
000050  4322              ORRS     r2,r2,r4
;;;711        /* Reset the Output N State */
;;;712        tmpccer &= (uint16_t)~TIM_CCER_CC1NE;
000052  f64f74fb          MOV      r4,#0xfffb
000056  4022              ANDS     r2,r2,r4
;;;713        
;;;714        /* Set the Output N State */
;;;715        tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
000058  888c              LDRH     r4,[r1,#4]
00005a  4322              ORRS     r2,r2,r4
;;;716        /* Reset the Output Compare and Output Compare N IDLE State */
;;;717        tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;
00005c  f64f64ff          MOV      r4,#0xfeff
000060  4023              ANDS     r3,r3,r4
;;;718        tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;
000062  f64f54ff          MOV      r4,#0xfdff
000066  4023              ANDS     r3,r3,r4
;;;719        /* Set the Output Idle state */
;;;720        tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
000068  8a0c              LDRH     r4,[r1,#0x10]
00006a  4323              ORRS     r3,r3,r4
;;;721        /* Set the Output N Idle state */
;;;722        tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
00006c  8a4c              LDRH     r4,[r1,#0x12]
00006e  4323              ORRS     r3,r3,r4
                  |L46.112|
;;;723      }
;;;724      /* Write to TIMx CR2 */
;;;725      TIMx->CR2 = tmpcr2;
000070  8083              STRH     r3,[r0,#4]
;;;726      
;;;727      /* Write to TIMx CCMR1 */
;;;728      TIMx->CCMR1 = tmpccmrx;
000072  f8a0c018          STRH     r12,[r0,#0x18]
;;;729      
;;;730      /* Set the Capture Compare Register value */
;;;731      TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
000076  688c              LDR      r4,[r1,#8]
000078  6344              STR      r4,[r0,#0x34]
;;;732      
;;;733      /* Write to TIMx CCER */
;;;734      TIMx->CCER = tmpccer;
00007a  8402              STRH     r2,[r0,#0x20]
;;;735    }
00007c  bd30              POP      {r4,r5,pc}
;;;736    
                          ENDP

00007e  0000              DCW      0x0000
                  |L46.128|
                          DCD      0x40010000
                  |L46.132|
                          DCD      0x40010400

                          AREA ||i.TIM_OC1NPolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC1NPolarityConfig PROC
;;;1611     */
;;;1612   void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
000000  460a              MOV      r2,r1
;;;1613   {
;;;1614     uint16_t tmpccer = 0;
000002  2100              MOVS     r1,#0
;;;1615     /* Check the parameters */
;;;1616     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;1617     assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
;;;1618      
;;;1619     tmpccer = TIMx->CCER;
000004  8c01              LDRH     r1,[r0,#0x20]
;;;1620   
;;;1621     /* Set or Reset the CC1NP Bit */
;;;1622     tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
000006  f64f73f7          MOV      r3,#0xfff7
00000a  4019              ANDS     r1,r1,r3
;;;1623     tmpccer |= TIM_OCNPolarity;
00000c  4311              ORRS     r1,r1,r2
;;;1624   
;;;1625     /* Write to TIMx CCER register */
;;;1626     TIMx->CCER = tmpccer;
00000e  8401              STRH     r1,[r0,#0x20]
;;;1627   }
000010  4770              BX       lr
;;;1628   
                          ENDP


                          AREA ||i.TIM_OC1PolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC1PolarityConfig PROC
;;;1584     */
;;;1585   void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000000  460a              MOV      r2,r1
;;;1586   {
;;;1587     uint16_t tmpccer = 0;
000002  2100              MOVS     r1,#0
;;;1588   
;;;1589     /* Check the parameters */
;;;1590     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1591     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1592   
;;;1593     tmpccer = TIMx->CCER;
000004  8c01              LDRH     r1,[r0,#0x20]
;;;1594   
;;;1595     /* Set or Reset the CC1P Bit */
;;;1596     tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
000006  f64f73fd          MOV      r3,#0xfffd
00000a  4019              ANDS     r1,r1,r3
;;;1597     tmpccer |= TIM_OCPolarity;
00000c  4311              ORRS     r1,r1,r2
;;;1598   
;;;1599     /* Write to TIMx CCER register */
;;;1600     TIMx->CCER = tmpccer;
00000e  8401              STRH     r1,[r0,#0x20]
;;;1601   }
000010  4770              BX       lr
;;;1602   
                          ENDP


                          AREA ||i.TIM_OC1PreloadConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC1PreloadConfig PROC
;;;1229     */
;;;1230   void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000000  460a              MOV      r2,r1
;;;1231   {
;;;1232     uint16_t tmpccmr1 = 0;
000002  2100              MOVS     r1,#0
;;;1233   
;;;1234     /* Check the parameters */
;;;1235     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1236     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1237   
;;;1238     tmpccmr1 = TIMx->CCMR1;
000004  8b01              LDRH     r1,[r0,#0x18]
;;;1239   
;;;1240     /* Reset the OC1PE Bit */
;;;1241     tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);
000006  f64f73f7          MOV      r3,#0xfff7
00000a  4019              ANDS     r1,r1,r3
;;;1242   
;;;1243     /* Enable or Disable the Output Compare Preload feature */
;;;1244     tmpccmr1 |= TIM_OCPreload;
00000c  4311              ORRS     r1,r1,r2
;;;1245   
;;;1246     /* Write to TIMx CCMR1 register */
;;;1247     TIMx->CCMR1 = tmpccmr1;
00000e  8301              STRH     r1,[r0,#0x18]
;;;1248   }
000010  4770              BX       lr
;;;1249   
                          ENDP


                          AREA ||i.TIM_OC2FastConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC2FastConfig PROC
;;;1377     */
;;;1378   void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000000  460a              MOV      r2,r1
;;;1379   {
;;;1380     uint16_t tmpccmr1 = 0;
000002  2100              MOVS     r1,#0
;;;1381   
;;;1382     /* Check the parameters */
;;;1383     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1384     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1385   
;;;1386     /* Get the TIMx CCMR1 register value */
;;;1387     tmpccmr1 = TIMx->CCMR1;
000004  8b01              LDRH     r1,[r0,#0x18]
;;;1388   
;;;1389     /* Reset the OC2FE Bit */
;;;1390     tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
000006  f64f33ff          MOV      r3,#0xfbff
00000a  4019              ANDS     r1,r1,r3
;;;1391   
;;;1392     /* Enable or Disable the Output Compare Fast Bit */
;;;1393     tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
00000c  0613              LSLS     r3,r2,#24
00000e  ea414113          ORR      r1,r1,r3,LSR #16
;;;1394   
;;;1395     /* Write to TIMx CCMR1 */
;;;1396     TIMx->CCMR1 = tmpccmr1;
000012  8301              STRH     r1,[r0,#0x18]
;;;1397   }
000014  4770              BX       lr
;;;1398   
                          ENDP


                          AREA ||i.TIM_OC2Init||, CODE, READONLY, ALIGN=2

                  TIM_OC2Init PROC
;;;745      */
;;;746    void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;747    {
;;;748      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
000002  f04f0c00          MOV      r12,#0
000006  2200              MOVS     r2,#0
000008  2300              MOVS     r3,#0
;;;749       
;;;750      /* Check the parameters */
;;;751      assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 
;;;752      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;753      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;754      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;755    
;;;756      /* Disable the Channel 2: Reset the CC2E Bit */
;;;757      TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
00000a  8c04              LDRH     r4,[r0,#0x20]
00000c  f64f75ef          MOV      r5,#0xffef
000010  402c              ANDS     r4,r4,r5
000012  8404              STRH     r4,[r0,#0x20]
;;;758      
;;;759      /* Get the TIMx CCER register value */  
;;;760      tmpccer = TIMx->CCER;
000014  8c02              LDRH     r2,[r0,#0x20]
;;;761      /* Get the TIMx CR2 register value */
;;;762      tmpcr2 =  TIMx->CR2;
000016  8883              LDRH     r3,[r0,#4]
;;;763      
;;;764      /* Get the TIMx CCMR1 register value */
;;;765      tmpccmrx = TIMx->CCMR1;
000018  f8b0c018          LDRH     r12,[r0,#0x18]
;;;766        
;;;767      /* Reset the Output Compare mode and Capture/Compare selection Bits */
;;;768      tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;
00001c  f64874ff          MOV      r4,#0x8fff
000020  ea0c0c04          AND      r12,r12,r4
;;;769      tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;
000024  f64f44ff          MOV      r4,#0xfcff
000028  ea0c0c04          AND      r12,r12,r4
;;;770      
;;;771      /* Select the Output Compare Mode */
;;;772      tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
00002c  880c              LDRH     r4,[r1,#0]
00002e  0624              LSLS     r4,r4,#24
000030  ea4c4c14          ORR      r12,r12,r4,LSR #16
;;;773      
;;;774      /* Reset the Output Polarity level */
;;;775      tmpccer &= (uint16_t)~TIM_CCER_CC2P;
000034  f64f74df          MOV      r4,#0xffdf
000038  4022              ANDS     r2,r2,r4
;;;776      /* Set the Output Compare Polarity */
;;;777      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
00003a  898c              LDRH     r4,[r1,#0xc]
00003c  0524              LSLS     r4,r4,#20
00003e  ea424214          ORR      r2,r2,r4,LSR #16
;;;778      
;;;779      /* Set the Output State */
;;;780      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
000042  884c              LDRH     r4,[r1,#2]
000044  0524              LSLS     r4,r4,#20
000046  ea424214          ORR      r2,r2,r4,LSR #16
;;;781        
;;;782      if((TIMx == TIM1) || (TIMx == TIM8))
00004a  4c14              LDR      r4,|L51.156|
00004c  42a0              CMP      r0,r4
00004e  d002              BEQ      |L51.86|
000050  4c13              LDR      r4,|L51.160|
000052  42a0              CMP      r0,r4
000054  d11b              BNE      |L51.142|
                  |L51.86|
;;;783      {
;;;784        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;785        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;786        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;787        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;788        
;;;789        /* Reset the Output N Polarity level */
;;;790        tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
000056  f64f747f          MOV      r4,#0xff7f
00005a  4022              ANDS     r2,r2,r4
;;;791        /* Set the Output N Polarity */
;;;792        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
00005c  89cc              LDRH     r4,[r1,#0xe]
00005e  0524              LSLS     r4,r4,#20
000060  ea424214          ORR      r2,r2,r4,LSR #16
;;;793        /* Reset the Output N State */
;;;794        tmpccer &= (uint16_t)~TIM_CCER_CC2NE;
000064  f64f74bf          MOV      r4,#0xffbf
000068  4022              ANDS     r2,r2,r4
;;;795        
;;;796        /* Set the Output N State */
;;;797        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
00006a  888c              LDRH     r4,[r1,#4]
00006c  0524              LSLS     r4,r4,#20
00006e  ea424214          ORR      r2,r2,r4,LSR #16
;;;798        /* Reset the Output Compare and Output Compare N IDLE State */
;;;799        tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;
000072  f64f34ff          MOV      r4,#0xfbff
000076  4023              ANDS     r3,r3,r4
;;;800        tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;
000078  f24f74ff          MOV      r4,#0xf7ff
00007c  4023              ANDS     r3,r3,r4
;;;801        /* Set the Output Idle state */
;;;802        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
00007e  8a0c              LDRH     r4,[r1,#0x10]
000080  04a4              LSLS     r4,r4,#18
000082  ea434314          ORR      r3,r3,r4,LSR #16
;;;803        /* Set the Output N Idle state */
;;;804        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
000086  8a4c              LDRH     r4,[r1,#0x12]
000088  04a4              LSLS     r4,r4,#18
00008a  ea434314          ORR      r3,r3,r4,LSR #16
                  |L51.142|
;;;805      }
;;;806      /* Write to TIMx CR2 */
;;;807      TIMx->CR2 = tmpcr2;
00008e  8083              STRH     r3,[r0,#4]
;;;808      
;;;809      /* Write to TIMx CCMR1 */
;;;810      TIMx->CCMR1 = tmpccmrx;
000090  f8a0c018          STRH     r12,[r0,#0x18]
;;;811      
;;;812      /* Set the Capture Compare Register value */
;;;813      TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
000094  688c              LDR      r4,[r1,#8]
000096  6384              STR      r4,[r0,#0x38]
;;;814      
;;;815      /* Write to TIMx CCER */
;;;816      TIMx->CCER = tmpccer;
000098  8402              STRH     r2,[r0,#0x20]
;;;817    }
00009a  bd30              POP      {r4,r5,pc}
;;;818    
                          ENDP

                  |L51.156|
                          DCD      0x40010000
                  |L51.160|
                          DCD      0x40010400

                          AREA ||i.TIM_OC2NPolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC2NPolarityConfig PROC
;;;1665     */
;;;1666   void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
000000  460a              MOV      r2,r1
;;;1667   {
;;;1668     uint16_t tmpccer = 0;
000002  2100              MOVS     r1,#0
;;;1669   
;;;1670     /* Check the parameters */
;;;1671     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;1672     assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
;;;1673     
;;;1674     tmpccer = TIMx->CCER;
000004  8c01              LDRH     r1,[r0,#0x20]
;;;1675   
;;;1676     /* Set or Reset the CC2NP Bit */
;;;1677     tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
000006  f64f737f          MOV      r3,#0xff7f
00000a  4019              ANDS     r1,r1,r3
;;;1678     tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
00000c  0513              LSLS     r3,r2,#20
00000e  ea414113          ORR      r1,r1,r3,LSR #16
;;;1679   
;;;1680     /* Write to TIMx CCER register */
;;;1681     TIMx->CCER = tmpccer;
000012  8401              STRH     r1,[r0,#0x20]
;;;1682   }
000014  4770              BX       lr
;;;1683   
                          ENDP


                          AREA ||i.TIM_OC2PolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC2PolarityConfig PROC
;;;1638     */
;;;1639   void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000000  460a              MOV      r2,r1
;;;1640   {
;;;1641     uint16_t tmpccer = 0;
000002  2100              MOVS     r1,#0
;;;1642   
;;;1643     /* Check the parameters */
;;;1644     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1645     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1646   
;;;1647     tmpccer = TIMx->CCER;
000004  8c01              LDRH     r1,[r0,#0x20]
;;;1648   
;;;1649     /* Set or Reset the CC2P Bit */
;;;1650     tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
000006  f64f73df          MOV      r3,#0xffdf
00000a  4019              ANDS     r1,r1,r3
;;;1651     tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
00000c  0513              LSLS     r3,r2,#20
00000e  ea414113          ORR      r1,r1,r3,LSR #16
;;;1652   
;;;1653     /* Write to TIMx CCER register */
;;;1654     TIMx->CCER = tmpccer;
000012  8401              STRH     r1,[r0,#0x20]
;;;1655   }
000014  4770              BX       lr
;;;1656   
                          ENDP


                          AREA ||i.TIM_OC2PreloadConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC2PreloadConfig PROC
;;;1259     */
;;;1260   void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000000  460a              MOV      r2,r1
;;;1261   {
;;;1262     uint16_t tmpccmr1 = 0;
000002  2100              MOVS     r1,#0
;;;1263   
;;;1264     /* Check the parameters */
;;;1265     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1266     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1267   
;;;1268     tmpccmr1 = TIMx->CCMR1;
000004  8b01              LDRH     r1,[r0,#0x18]
;;;1269   
;;;1270     /* Reset the OC2PE Bit */
;;;1271     tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);
000006  f24f73ff          MOV      r3,#0xf7ff
00000a  4019              ANDS     r1,r1,r3
;;;1272   
;;;1273     /* Enable or Disable the Output Compare Preload feature */
;;;1274     tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
00000c  0613              LSLS     r3,r2,#24
00000e  ea414113          ORR      r1,r1,r3,LSR #16
;;;1275   
;;;1276     /* Write to TIMx CCMR1 register */
;;;1277     TIMx->CCMR1 = tmpccmr1;
000012  8301              STRH     r1,[r0,#0x18]
;;;1278   }
000014  4770              BX       lr
;;;1279   
                          ENDP


                          AREA ||i.TIM_OC3FastConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC3FastConfig PROC
;;;1407     */
;;;1408   void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000000  460a              MOV      r2,r1
;;;1409   {
;;;1410     uint16_t tmpccmr2 = 0;
000002  2100              MOVS     r1,#0
;;;1411     
;;;1412     /* Check the parameters */
;;;1413     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1414     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1415   
;;;1416     /* Get the TIMx CCMR2 register value */
;;;1417     tmpccmr2 = TIMx->CCMR2;
000004  8b81              LDRH     r1,[r0,#0x1c]
;;;1418   
;;;1419     /* Reset the OC3FE Bit */
;;;1420     tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;
000006  f64f73fb          MOV      r3,#0xfffb
00000a  4019              ANDS     r1,r1,r3
;;;1421   
;;;1422     /* Enable or Disable the Output Compare Fast Bit */
;;;1423     tmpccmr2 |= TIM_OCFast;
00000c  4311              ORRS     r1,r1,r2
;;;1424   
;;;1425     /* Write to TIMx CCMR2 */
;;;1426     TIMx->CCMR2 = tmpccmr2;
00000e  8381              STRH     r1,[r0,#0x1c]
;;;1427   }
000010  4770              BX       lr
;;;1428   
                          ENDP


                          AREA ||i.TIM_OC3Init||, CODE, READONLY, ALIGN=2

                  TIM_OC3Init PROC
;;;826      */
;;;827    void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;828    {
;;;829      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
000002  f04f0c00          MOV      r12,#0
000006  2200              MOVS     r2,#0
000008  2300              MOVS     r3,#0
;;;830       
;;;831      /* Check the parameters */
;;;832      assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
;;;833      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;834      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;835      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;836    
;;;837      /* Disable the Channel 3: Reset the CC2E Bit */
;;;838      TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
00000a  8c04              LDRH     r4,[r0,#0x20]
00000c  f64f65ff          MOV      r5,#0xfeff
000010  402c              ANDS     r4,r4,r5
000012  8404              STRH     r4,[r0,#0x20]
;;;839      
;;;840      /* Get the TIMx CCER register value */
;;;841      tmpccer = TIMx->CCER;
000014  8c02              LDRH     r2,[r0,#0x20]
;;;842      /* Get the TIMx CR2 register value */
;;;843      tmpcr2 =  TIMx->CR2;
000016  8883              LDRH     r3,[r0,#4]
;;;844      
;;;845      /* Get the TIMx CCMR2 register value */
;;;846      tmpccmrx = TIMx->CCMR2;
000018  f8b0c01c          LDRH     r12,[r0,#0x1c]
;;;847        
;;;848      /* Reset the Output Compare mode and Capture/Compare selection Bits */
;;;849      tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;
00001c  f64f748f          MOV      r4,#0xff8f
000020  ea0c0c04          AND      r12,r12,r4
;;;850      tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S;  
000024  f64f74fc          MOV      r4,#0xfffc
000028  ea0c0c04          AND      r12,r12,r4
;;;851      /* Select the Output Compare Mode */
;;;852      tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00002c  880c              LDRH     r4,[r1,#0]
00002e  ea440c0c          ORR      r12,r4,r12
;;;853      
;;;854      /* Reset the Output Polarity level */
;;;855      tmpccer &= (uint16_t)~TIM_CCER_CC3P;
000032  f64f54ff          MOV      r4,#0xfdff
000036  4022              ANDS     r2,r2,r4
;;;856      /* Set the Output Compare Polarity */
;;;857      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
000038  898c              LDRH     r4,[r1,#0xc]
00003a  0624              LSLS     r4,r4,#24
00003c  ea424214          ORR      r2,r2,r4,LSR #16
;;;858      
;;;859      /* Set the Output State */
;;;860      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
000040  884c              LDRH     r4,[r1,#2]
000042  0624              LSLS     r4,r4,#24
000044  ea424214          ORR      r2,r2,r4,LSR #16
;;;861        
;;;862      if((TIMx == TIM1) || (TIMx == TIM8))
000048  4c14              LDR      r4,|L56.156|
00004a  42a0              CMP      r0,r4
00004c  d002              BEQ      |L56.84|
00004e  4c14              LDR      r4,|L56.160|
000050  42a0              CMP      r0,r4
000052  d11b              BNE      |L56.140|
                  |L56.84|
;;;863      {
;;;864        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;865        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;866        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;867        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;868        
;;;869        /* Reset the Output N Polarity level */
;;;870        tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
000054  f24f74ff          MOV      r4,#0xf7ff
000058  4022              ANDS     r2,r2,r4
;;;871        /* Set the Output N Polarity */
;;;872        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
00005a  89cc              LDRH     r4,[r1,#0xe]
00005c  0624              LSLS     r4,r4,#24
00005e  ea424214          ORR      r2,r2,r4,LSR #16
;;;873        /* Reset the Output N State */
;;;874        tmpccer &= (uint16_t)~TIM_CCER_CC3NE;
000062  f64f34ff          MOV      r4,#0xfbff
000066  4022              ANDS     r2,r2,r4
;;;875        
;;;876        /* Set the Output N State */
;;;877        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
000068  888c              LDRH     r4,[r1,#4]
00006a  0624              LSLS     r4,r4,#24
00006c  ea424214          ORR      r2,r2,r4,LSR #16
;;;878        /* Reset the Output Compare and Output Compare N IDLE State */
;;;879        tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;
000070  f64e74ff          MOV      r4,#0xefff
000074  4023              ANDS     r3,r3,r4
;;;880        tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;
000076  f64d74ff          MOV      r4,#0xdfff
00007a  4023              ANDS     r3,r3,r4
;;;881        /* Set the Output Idle state */
;;;882        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
00007c  8a0c              LDRH     r4,[r1,#0x10]
00007e  0524              LSLS     r4,r4,#20
000080  ea434314          ORR      r3,r3,r4,LSR #16
;;;883        /* Set the Output N Idle state */
;;;884        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
000084  8a4c              LDRH     r4,[r1,#0x12]
000086  0524              LSLS     r4,r4,#20
000088  ea434314          ORR      r3,r3,r4,LSR #16
                  |L56.140|
;;;885      }
;;;886      /* Write to TIMx CR2 */
;;;887      TIMx->CR2 = tmpcr2;
00008c  8083              STRH     r3,[r0,#4]
;;;888      
;;;889      /* Write to TIMx CCMR2 */
;;;890      TIMx->CCMR2 = tmpccmrx;
00008e  f8a0c01c          STRH     r12,[r0,#0x1c]
;;;891      
;;;892      /* Set the Capture Compare Register value */
;;;893      TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
000092  688c              LDR      r4,[r1,#8]
000094  63c4              STR      r4,[r0,#0x3c]
;;;894      
;;;895      /* Write to TIMx CCER */
;;;896      TIMx->CCER = tmpccer;
000096  8402              STRH     r2,[r0,#0x20]
;;;897    }
000098  bd30              POP      {r4,r5,pc}
;;;898    
                          ENDP

00009a  0000              DCW      0x0000
                  |L56.156|
                          DCD      0x40010000
                  |L56.160|
                          DCD      0x40010400

                          AREA ||i.TIM_OC3NPolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC3NPolarityConfig PROC
;;;1719     */
;;;1720   void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
000000  460a              MOV      r2,r1
;;;1721   {
;;;1722     uint16_t tmpccer = 0;
000002  2100              MOVS     r1,#0
;;;1723    
;;;1724     /* Check the parameters */
;;;1725     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;1726     assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
;;;1727       
;;;1728     tmpccer = TIMx->CCER;
000004  8c01              LDRH     r1,[r0,#0x20]
;;;1729   
;;;1730     /* Set or Reset the CC3NP Bit */
;;;1731     tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
000006  f24f73ff          MOV      r3,#0xf7ff
00000a  4019              ANDS     r1,r1,r3
;;;1732     tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
00000c  0613              LSLS     r3,r2,#24
00000e  ea414113          ORR      r1,r1,r3,LSR #16
;;;1733   
;;;1734     /* Write to TIMx CCER register */
;;;1735     TIMx->CCER = tmpccer;
000012  8401              STRH     r1,[r0,#0x20]
;;;1736   }
000014  4770              BX       lr
;;;1737   
                          ENDP


                          AREA ||i.TIM_OC3PolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC3PolarityConfig PROC
;;;1692     */
;;;1693   void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000000  460a              MOV      r2,r1
;;;1694   {
;;;1695     uint16_t tmpccer = 0;
000002  2100              MOVS     r1,#0
;;;1696   
;;;1697     /* Check the parameters */
;;;1698     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1699     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1700   
;;;1701     tmpccer = TIMx->CCER;
000004  8c01              LDRH     r1,[r0,#0x20]
;;;1702   
;;;1703     /* Set or Reset the CC3P Bit */
;;;1704     tmpccer &= (uint16_t)~TIM_CCER_CC3P;
000006  f64f53ff          MOV      r3,#0xfdff
00000a  4019              ANDS     r1,r1,r3
;;;1705     tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
00000c  0613              LSLS     r3,r2,#24
00000e  ea414113          ORR      r1,r1,r3,LSR #16
;;;1706   
;;;1707     /* Write to TIMx CCER register */
;;;1708     TIMx->CCER = tmpccer;
000012  8401              STRH     r1,[r0,#0x20]
;;;1709   }
000014  4770              BX       lr
;;;1710   
                          ENDP


                          AREA ||i.TIM_OC3PreloadConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC3PreloadConfig PROC
;;;1288     */
;;;1289   void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000000  460a              MOV      r2,r1
;;;1290   {
;;;1291     uint16_t tmpccmr2 = 0;
000002  2100              MOVS     r1,#0
;;;1292   
;;;1293     /* Check the parameters */
;;;1294     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1295     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1296   
;;;1297     tmpccmr2 = TIMx->CCMR2;
000004  8b81              LDRH     r1,[r0,#0x1c]
;;;1298   
;;;1299     /* Reset the OC3PE Bit */
;;;1300     tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);
000006  f64f73f7          MOV      r3,#0xfff7
00000a  4019              ANDS     r1,r1,r3
;;;1301   
;;;1302     /* Enable or Disable the Output Compare Preload feature */
;;;1303     tmpccmr2 |= TIM_OCPreload;
00000c  4311              ORRS     r1,r1,r2
;;;1304   
;;;1305     /* Write to TIMx CCMR2 register */
;;;1306     TIMx->CCMR2 = tmpccmr2;
00000e  8381              STRH     r1,[r0,#0x1c]
;;;1307   }
000010  4770              BX       lr
;;;1308   
                          ENDP


                          AREA ||i.TIM_OC4FastConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC4FastConfig PROC
;;;1437     */
;;;1438   void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000000  460a              MOV      r2,r1
;;;1439   {
;;;1440     uint16_t tmpccmr2 = 0;
000002  2100              MOVS     r1,#0
;;;1441   
;;;1442     /* Check the parameters */
;;;1443     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1444     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1445   
;;;1446     /* Get the TIMx CCMR2 register value */
;;;1447     tmpccmr2 = TIMx->CCMR2;
000004  8b81              LDRH     r1,[r0,#0x1c]
;;;1448   
;;;1449     /* Reset the OC4FE Bit */
;;;1450     tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
000006  f64f33ff          MOV      r3,#0xfbff
00000a  4019              ANDS     r1,r1,r3
;;;1451   
;;;1452     /* Enable or Disable the Output Compare Fast Bit */
;;;1453     tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
00000c  0613              LSLS     r3,r2,#24
00000e  ea414113          ORR      r1,r1,r3,LSR #16
;;;1454   
;;;1455     /* Write to TIMx CCMR2 */
;;;1456     TIMx->CCMR2 = tmpccmr2;
000012  8381              STRH     r1,[r0,#0x1c]
;;;1457   }
000014  4770              BX       lr
;;;1458   
                          ENDP


                          AREA ||i.TIM_OC4Init||, CODE, READONLY, ALIGN=2

                  TIM_OC4Init PROC
;;;906      */
;;;907    void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;908    {
;;;909      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
000002  2200              MOVS     r2,#0
000004  2300              MOVS     r3,#0
000006  4694              MOV      r12,r2
;;;910       
;;;911      /* Check the parameters */
;;;912      assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
;;;913      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;914      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;915      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;916    
;;;917      /* Disable the Channel 4: Reset the CC4E Bit */
;;;918      TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
000008  8c04              LDRH     r4,[r0,#0x20]
00000a  f64e75ff          MOV      r5,#0xefff
00000e  402c              ANDS     r4,r4,r5
000010  8404              STRH     r4,[r0,#0x20]
;;;919      
;;;920      /* Get the TIMx CCER register value */
;;;921      tmpccer = TIMx->CCER;
000012  8c03              LDRH     r3,[r0,#0x20]
;;;922      /* Get the TIMx CR2 register value */
;;;923      tmpcr2 =  TIMx->CR2;
000014  f8b0c004          LDRH     r12,[r0,#4]
;;;924      
;;;925      /* Get the TIMx CCMR2 register value */
;;;926      tmpccmrx = TIMx->CCMR2;
000018  8b82              LDRH     r2,[r0,#0x1c]
;;;927        
;;;928      /* Reset the Output Compare mode and Capture/Compare selection Bits */
;;;929      tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;
00001a  f64874ff          MOV      r4,#0x8fff
00001e  4022              ANDS     r2,r2,r4
;;;930      tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;
000020  f64f44ff          MOV      r4,#0xfcff
000024  4022              ANDS     r2,r2,r4
;;;931      
;;;932      /* Select the Output Compare Mode */
;;;933      tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
000026  880c              LDRH     r4,[r1,#0]
000028  0624              LSLS     r4,r4,#24
00002a  ea424214          ORR      r2,r2,r4,LSR #16
;;;934      
;;;935      /* Reset the Output Polarity level */
;;;936      tmpccer &= (uint16_t)~TIM_CCER_CC4P;
00002e  f64d74ff          MOV      r4,#0xdfff
000032  4023              ANDS     r3,r3,r4
;;;937      /* Set the Output Compare Polarity */
;;;938      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
000034  898c              LDRH     r4,[r1,#0xc]
000036  0724              LSLS     r4,r4,#28
000038  ea434314          ORR      r3,r3,r4,LSR #16
;;;939      
;;;940      /* Set the Output State */
;;;941      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
00003c  884c              LDRH     r4,[r1,#2]
00003e  0724              LSLS     r4,r4,#28
000040  ea434314          ORR      r3,r3,r4,LSR #16
;;;942      
;;;943      if((TIMx == TIM1) || (TIMx == TIM8))
000044  4c0a              LDR      r4,|L61.112|
000046  42a0              CMP      r0,r4
000048  d002              BEQ      |L61.80|
00004a  4c0a              LDR      r4,|L61.116|
00004c  42a0              CMP      r0,r4
00004e  d107              BNE      |L61.96|
                  |L61.80|
;;;944      {
;;;945        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;946        /* Reset the Output Compare IDLE State */
;;;947        tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;
000050  f64b74ff          MOV      r4,#0xbfff
000054  ea0c0c04          AND      r12,r12,r4
;;;948        /* Set the Output Idle state */
;;;949        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
000058  8a0c              LDRH     r4,[r1,#0x10]
00005a  05a4              LSLS     r4,r4,#22
00005c  ea4c4c14          ORR      r12,r12,r4,LSR #16
                  |L61.96|
;;;950      }
;;;951      /* Write to TIMx CR2 */
;;;952      TIMx->CR2 = tmpcr2;
000060  f8a0c004          STRH     r12,[r0,#4]
;;;953      
;;;954      /* Write to TIMx CCMR2 */  
;;;955      TIMx->CCMR2 = tmpccmrx;
000064  8382              STRH     r2,[r0,#0x1c]
;;;956        
;;;957      /* Set the Capture Compare Register value */
;;;958      TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
000066  688c              LDR      r4,[r1,#8]
000068  6404              STR      r4,[r0,#0x40]
;;;959      
;;;960      /* Write to TIMx CCER */
;;;961      TIMx->CCER = tmpccer;
00006a  8403              STRH     r3,[r0,#0x20]
;;;962    }
00006c  bd30              POP      {r4,r5,pc}
;;;963    
                          ENDP

00006e  0000              DCW      0x0000
                  |L61.112|
                          DCD      0x40010000
                  |L61.116|
                          DCD      0x40010400

                          AREA ||i.TIM_OC4PolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC4PolarityConfig PROC
;;;1746     */
;;;1747   void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000000  460a              MOV      r2,r1
;;;1748   {
;;;1749     uint16_t tmpccer = 0;
000002  2100              MOVS     r1,#0
;;;1750   
;;;1751     /* Check the parameters */
;;;1752     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1753     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1754   
;;;1755     tmpccer = TIMx->CCER;
000004  8c01              LDRH     r1,[r0,#0x20]
;;;1756   
;;;1757     /* Set or Reset the CC4P Bit */
;;;1758     tmpccer &= (uint16_t)~TIM_CCER_CC4P;
000006  f64d73ff          MOV      r3,#0xdfff
00000a  4019              ANDS     r1,r1,r3
;;;1759     tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
00000c  0713              LSLS     r3,r2,#28
00000e  ea414113          ORR      r1,r1,r3,LSR #16
;;;1760   
;;;1761     /* Write to TIMx CCER register */
;;;1762     TIMx->CCER = tmpccer;
000012  8401              STRH     r1,[r0,#0x20]
;;;1763   }
000014  4770              BX       lr
;;;1764   
                          ENDP


                          AREA ||i.TIM_OC4PreloadConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC4PreloadConfig PROC
;;;1317     */
;;;1318   void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000000  460a              MOV      r2,r1
;;;1319   {
;;;1320     uint16_t tmpccmr2 = 0;
000002  2100              MOVS     r1,#0
;;;1321   
;;;1322     /* Check the parameters */
;;;1323     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1324     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1325   
;;;1326     tmpccmr2 = TIMx->CCMR2;
000004  8b81              LDRH     r1,[r0,#0x1c]
;;;1327   
;;;1328     /* Reset the OC4PE Bit */
;;;1329     tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);
000006  f24f73ff          MOV      r3,#0xf7ff
00000a  4019              ANDS     r1,r1,r3
;;;1330   
;;;1331     /* Enable or Disable the Output Compare Preload feature */
;;;1332     tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
00000c  0613              LSLS     r3,r2,#24
00000e  ea414113          ORR      r1,r1,r3,LSR #16
;;;1333   
;;;1334     /* Write to TIMx CCMR2 register */
;;;1335     TIMx->CCMR2 = tmpccmr2;
000012  8381              STRH     r1,[r0,#0x1c]
;;;1336   }
000014  4770              BX       lr
;;;1337   
                          ENDP


                          AREA ||i.TIM_OCStructInit||, CODE, READONLY, ALIGN=1

                  TIM_OCStructInit PROC
;;;969      */
;;;970    void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
000000  2100              MOVS     r1,#0
;;;971    {
;;;972      /* Set the default configuration */
;;;973      TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
000002  8001              STRH     r1,[r0,#0]
;;;974      TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
000004  8041              STRH     r1,[r0,#2]
;;;975      TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
000006  8081              STRH     r1,[r0,#4]
;;;976      TIM_OCInitStruct->TIM_Pulse = 0x00000000;
000008  6081              STR      r1,[r0,#8]
;;;977      TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
00000a  8181              STRH     r1,[r0,#0xc]
;;;978      TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
00000c  81c1              STRH     r1,[r0,#0xe]
;;;979      TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
00000e  8201              STRH     r1,[r0,#0x10]
;;;980      TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
000010  8241              STRH     r1,[r0,#0x12]
;;;981    }
000012  4770              BX       lr
;;;982    
                          ENDP


                          AREA ||i.TIM_PWMIConfig||, CODE, READONLY, ALIGN=1

                  TIM_PWMIConfig PROC
;;;1964     */
;;;1965   void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
000000  e92d41f0          PUSH     {r4-r8,lr}
;;;1966   {
000004  4605              MOV      r5,r0
000006  460c              MOV      r4,r1
;;;1967     uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
000008  2600              MOVS     r6,#0
;;;1968     uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
00000a  2701              MOVS     r7,#1
;;;1969   
;;;1970     /* Check the parameters */
;;;1971     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1972   
;;;1973     /* Select the Opposite Input Polarity */
;;;1974     if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
00000c  8860              LDRH     r0,[r4,#2]
00000e  b908              CBNZ     r0,|L65.20|
;;;1975     {
;;;1976       icoppositepolarity = TIM_ICPolarity_Falling;
000010  2602              MOVS     r6,#2
000012  e000              B        |L65.22|
                  |L65.20|
;;;1977     }
;;;1978     else
;;;1979     {
;;;1980       icoppositepolarity = TIM_ICPolarity_Rising;
000014  2600              MOVS     r6,#0
                  |L65.22|
;;;1981     }
;;;1982     /* Select the Opposite Input */
;;;1983     if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
000016  88a0              LDRH     r0,[r4,#4]
000018  2801              CMP      r0,#1
00001a  d101              BNE      |L65.32|
;;;1984     {
;;;1985       icoppositeselection = TIM_ICSelection_IndirectTI;
00001c  2702              MOVS     r7,#2
00001e  e000              B        |L65.34|
                  |L65.32|
;;;1986     }
;;;1987     else
;;;1988     {
;;;1989       icoppositeselection = TIM_ICSelection_DirectTI;
000020  2701              MOVS     r7,#1
                  |L65.34|
;;;1990     }
;;;1991     if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
000022  8820              LDRH     r0,[r4,#0]
000024  b9a0              CBNZ     r0,|L65.80|
;;;1992     {
;;;1993       /* TI1 Configuration */
;;;1994       TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
000026  8923              LDRH     r3,[r4,#8]
000028  88a2              LDRH     r2,[r4,#4]
00002a  8861              LDRH     r1,[r4,#2]
00002c  4628              MOV      r0,r5
00002e  f7fffffe          BL       TI1_Config
;;;1995                  TIM_ICInitStruct->TIM_ICFilter);
;;;1996       /* Set the Input Capture Prescaler value */
;;;1997       TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000032  88e1              LDRH     r1,[r4,#6]
000034  4628              MOV      r0,r5
000036  f7fffffe          BL       TIM_SetIC1Prescaler
;;;1998       /* TI2 Configuration */
;;;1999       TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
00003a  8923              LDRH     r3,[r4,#8]
00003c  463a              MOV      r2,r7
00003e  4631              MOV      r1,r6
000040  4628              MOV      r0,r5
000042  f7fffffe          BL       TI2_Config
;;;2000       /* Set the Input Capture Prescaler value */
;;;2001       TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000046  88e1              LDRH     r1,[r4,#6]
000048  4628              MOV      r0,r5
00004a  f7fffffe          BL       TIM_SetIC2Prescaler
00004e  e013              B        |L65.120|
                  |L65.80|
;;;2002     }
;;;2003     else
;;;2004     { 
;;;2005       /* TI2 Configuration */
;;;2006       TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
000050  8923              LDRH     r3,[r4,#8]
000052  88a2              LDRH     r2,[r4,#4]
000054  8861              LDRH     r1,[r4,#2]
000056  4628              MOV      r0,r5
000058  f7fffffe          BL       TI2_Config
;;;2007                  TIM_ICInitStruct->TIM_ICFilter);
;;;2008       /* Set the Input Capture Prescaler value */
;;;2009       TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00005c  88e1              LDRH     r1,[r4,#6]
00005e  4628              MOV      r0,r5
000060  f7fffffe          BL       TIM_SetIC2Prescaler
;;;2010       /* TI1 Configuration */
;;;2011       TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
000064  8923              LDRH     r3,[r4,#8]
000066  463a              MOV      r2,r7
000068  4631              MOV      r1,r6
00006a  4628              MOV      r0,r5
00006c  f7fffffe          BL       TI1_Config
;;;2012       /* Set the Input Capture Prescaler value */
;;;2013       TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000070  88e1              LDRH     r1,[r4,#6]
000072  4628              MOV      r0,r5
000074  f7fffffe          BL       TIM_SetIC1Prescaler
                  |L65.120|
;;;2014     }
;;;2015   }
000078  e8bd81f0          POP      {r4-r8,pc}
;;;2016   
                          ENDP


                          AREA ||i.TIM_PrescalerConfig||, CODE, READONLY, ALIGN=1

                  TIM_PrescalerConfig PROC
;;;353      */
;;;354    void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
000000  8501              STRH     r1,[r0,#0x28]
;;;355    {
;;;356      /* Check the parameters */
;;;357      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;358      assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
;;;359      /* Set the Prescaler value */
;;;360      TIMx->PSC = Prescaler;
;;;361      /* Set or reset the UG Bit */
;;;362      TIMx->EGR = TIM_PSCReloadMode;
000002  8282              STRH     r2,[r0,#0x14]
;;;363    }
000004  4770              BX       lr
;;;364    
                          ENDP


                          AREA ||i.TIM_RemapConfig||, CODE, READONLY, ALIGN=1

                  TIM_RemapConfig PROC
;;;3159     */
;;;3160   void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
000000  f8a01050          STRH     r1,[r0,#0x50]
;;;3161   {
;;;3162    /* Check the parameters */
;;;3163     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;3164     assert_param(IS_TIM_REMAP(TIM_Remap));
;;;3165   
;;;3166     /* Set the Timer remapping configuration */
;;;3167     TIMx->OR =  TIM_Remap;
;;;3168   }
000004  4770              BX       lr
;;;3169   /**
                          ENDP


                          AREA ||i.TIM_SelectCCDMA||, CODE, READONLY, ALIGN=1

                  TIM_SelectCCDMA PROC
;;;2633     */
;;;2634   void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  b121              CBZ      r1,|L68.12|
;;;2635   {
;;;2636     /* Check the parameters */
;;;2637     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2638     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2639   
;;;2640     if (NewState != DISABLE)
;;;2641     {
;;;2642       /* Set the CCDS Bit */
;;;2643       TIMx->CR2 |= TIM_CR2_CCDS;
000002  8882              LDRH     r2,[r0,#4]
000004  f0420208          ORR      r2,r2,#8
000008  8082              STRH     r2,[r0,#4]
00000a  e004              B        |L68.22|
                  |L68.12|
;;;2644     }
;;;2645     else
;;;2646     {
;;;2647       /* Reset the CCDS Bit */
;;;2648       TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
00000c  8882              LDRH     r2,[r0,#4]
00000e  f64f73f7          MOV      r3,#0xfff7
000012  401a              ANDS     r2,r2,r3
000014  8082              STRH     r2,[r0,#4]
                  |L68.22|
;;;2649     }
;;;2650   }
000016  4770              BX       lr
;;;2651   /**
                          ENDP


                          AREA ||i.TIM_SelectCOM||, CODE, READONLY, ALIGN=1

                  TIM_SelectCOM PROC
;;;2279     */
;;;2280   void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  b121              CBZ      r1,|L69.12|
;;;2281   {
;;;2282     /* Check the parameters */
;;;2283     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;2284     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2285   
;;;2286     if (NewState != DISABLE)
;;;2287     {
;;;2288       /* Set the COM Bit */
;;;2289       TIMx->CR2 |= TIM_CR2_CCUS;
000002  8882              LDRH     r2,[r0,#4]
000004  f0420204          ORR      r2,r2,#4
000008  8082              STRH     r2,[r0,#4]
00000a  e004              B        |L69.22|
                  |L69.12|
;;;2290     }
;;;2291     else
;;;2292     {
;;;2293       /* Reset the COM Bit */
;;;2294       TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
00000c  8882              LDRH     r2,[r0,#4]
00000e  f64f73fb          MOV      r3,#0xfffb
000012  401a              ANDS     r2,r2,r3
000014  8082              STRH     r2,[r0,#4]
                  |L69.22|
;;;2295     }
;;;2296   }
000016  4770              BX       lr
;;;2297   
                          ENDP


                          AREA ||i.TIM_SelectHallSensor||, CODE, READONLY, ALIGN=1

                  TIM_SelectHallSensor PROC
;;;3108     */
;;;3109   void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  b121              CBZ      r1,|L70.12|
;;;3110   {
;;;3111     /* Check the parameters */
;;;3112     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;3113     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;3114   
;;;3115     if (NewState != DISABLE)
;;;3116     {
;;;3117       /* Set the TI1S Bit */
;;;3118       TIMx->CR2 |= TIM_CR2_TI1S;
000002  8882              LDRH     r2,[r0,#4]
000004  f0420280          ORR      r2,r2,#0x80
000008  8082              STRH     r2,[r0,#4]
00000a  e004              B        |L70.22|
                  |L70.12|
;;;3119     }
;;;3120     else
;;;3121     {
;;;3122       /* Reset the TI1S Bit */
;;;3123       TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
00000c  8882              LDRH     r2,[r0,#4]
00000e  f64f737f          MOV      r3,#0xff7f
000012  401a              ANDS     r2,r2,r3
000014  8082              STRH     r2,[r0,#4]
                  |L70.22|
;;;3124     }
;;;3125   }
000016  4770              BX       lr
;;;3126   /**
                          ENDP


                          AREA ||i.TIM_SelectInputTrigger||, CODE, READONLY, ALIGN=1

                  TIM_SelectInputTrigger PROC
;;;2878     */
;;;2879   void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
000000  460a              MOV      r2,r1
;;;2880   {
;;;2881     uint16_t tmpsmcr = 0;
000002  2100              MOVS     r1,#0
;;;2882   
;;;2883     /* Check the parameters */
;;;2884     assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
;;;2885     assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
;;;2886   
;;;2887     /* Get the TIMx SMCR register value */
;;;2888     tmpsmcr = TIMx->SMCR;
000004  8901              LDRH     r1,[r0,#8]
;;;2889   
;;;2890     /* Reset the TS Bits */
;;;2891     tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
000006  f64f738f          MOV      r3,#0xff8f
00000a  4019              ANDS     r1,r1,r3
;;;2892   
;;;2893     /* Set the Input Trigger source */
;;;2894     tmpsmcr |= TIM_InputTriggerSource;
00000c  4311              ORRS     r1,r1,r2
;;;2895   
;;;2896     /* Write to TIMx SMCR */
;;;2897     TIMx->SMCR = tmpsmcr;
00000e  8101              STRH     r1,[r0,#8]
;;;2898   }
000010  4770              BX       lr
;;;2899   
                          ENDP


                          AREA ||i.TIM_SelectMasterSlaveMode||, CODE, READONLY, ALIGN=1

                  TIM_SelectMasterSlaveMode PROC
;;;2968     */
;;;2969   void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
000000  8902              LDRH     r2,[r0,#8]
;;;2970   {
;;;2971     /* Check the parameters */
;;;2972     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2973     assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
;;;2974   
;;;2975     /* Reset the MSM Bit */
;;;2976     TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
000002  f64f737f          MOV      r3,#0xff7f
000006  401a              ANDS     r2,r2,r3
000008  8102              STRH     r2,[r0,#8]
;;;2977     
;;;2978     /* Set or Reset the MSM Bit */
;;;2979     TIMx->SMCR |= TIM_MasterSlaveMode;
00000a  8902              LDRH     r2,[r0,#8]
00000c  430a              ORRS     r2,r2,r1
00000e  8102              STRH     r2,[r0,#8]
;;;2980   }
000010  4770              BX       lr
;;;2981   
                          ENDP


                          AREA ||i.TIM_SelectOCxM||, CODE, READONLY, ALIGN=1

                  TIM_SelectOCxM PROC
;;;1005     */
;;;1006   void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
000000  b530              PUSH     {r4,r5,lr}
;;;1007   {
000002  4603              MOV      r3,r0
;;;1008     uint32_t tmp = 0;
000004  2000              MOVS     r0,#0
;;;1009     uint16_t tmp1 = 0;
000006  4684              MOV      r12,r0
;;;1010   
;;;1011     /* Check the parameters */
;;;1012     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1013     assert_param(IS_TIM_CHANNEL(TIM_Channel));
;;;1014     assert_param(IS_TIM_OCM(TIM_OCMode));
;;;1015   
;;;1016     tmp = (uint32_t) TIMx;
000008  4618              MOV      r0,r3
;;;1017     tmp += CCMR_OFFSET;
00000a  3018              ADDS     r0,r0,#0x18
;;;1018   
;;;1019     tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
00000c  2401              MOVS     r4,#1
00000e  408c              LSLS     r4,r4,r1
000010  fa1ffc84          UXTH     r12,r4
;;;1020   
;;;1021     /* Disable the Channel: Reset the CCxE Bit */
;;;1022     TIMx->CCER &= (uint16_t) ~tmp1;
000014  8c1c              LDRH     r4,[r3,#0x20]
000016  ea6f050c          MVN      r5,r12
00001a  b2ad              UXTH     r5,r5
00001c  402c              ANDS     r4,r4,r5
00001e  841c              STRH     r4,[r3,#0x20]
;;;1023   
;;;1024     if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
000020  b109              CBZ      r1,|L73.38|
000022  2908              CMP      r1,#8
000024  d10a              BNE      |L73.60|
                  |L73.38|
;;;1025     {
;;;1026       tmp += (TIM_Channel>>1);
000026  eb000061          ADD      r0,r0,r1,ASR #1
;;;1027   
;;;1028       /* Reset the OCxM bits in the CCMRx register */
;;;1029       *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
00002a  6804              LDR      r4,[r0,#0]
00002c  f64f758f          MOV      r5,#0xff8f
000030  402c              ANDS     r4,r4,r5
000032  6004              STR      r4,[r0,#0]
;;;1030      
;;;1031       /* Configure the OCxM bits in the CCMRx register */
;;;1032       *(__IO uint32_t *) tmp |= TIM_OCMode;
000034  6804              LDR      r4,[r0,#0]
000036  4314              ORRS     r4,r4,r2
000038  6004              STR      r4,[r0,#0]
00003a  e00d              B        |L73.88|
                  |L73.60|
;;;1033     }
;;;1034     else
;;;1035     {
;;;1036       tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
00003c  1f0c              SUBS     r4,r1,#4
00003e  b2a4              UXTH     r4,r4
000040  eb000064          ADD      r0,r0,r4,ASR #1
;;;1037   
;;;1038       /* Reset the OCxM bits in the CCMRx register */
;;;1039       *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
000044  6804              LDR      r4,[r0,#0]
000046  f64875ff          MOV      r5,#0x8fff
00004a  402c              ANDS     r4,r4,r5
00004c  6004              STR      r4,[r0,#0]
;;;1040       
;;;1041       /* Configure the OCxM bits in the CCMRx register */
;;;1042       *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
00004e  6804              LDR      r4,[r0,#0]
000050  0615              LSLS     r5,r2,#24
000052  ea444415          ORR      r4,r4,r5,LSR #16
000056  6004              STR      r4,[r0,#0]
                  |L73.88|
;;;1043     }
;;;1044   }
000058  bd30              POP      {r4,r5,pc}
;;;1045   
                          ENDP


                          AREA ||i.TIM_SelectOnePulseMode||, CODE, READONLY, ALIGN=1

                  TIM_SelectOnePulseMode PROC
;;;542      */
;;;543    void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
000000  8802              LDRH     r2,[r0,#0]
;;;544    {
;;;545      /* Check the parameters */
;;;546      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;547      assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
;;;548    
;;;549      /* Reset the OPM Bit */
;;;550      TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
000002  f64f73f7          MOV      r3,#0xfff7
000006  401a              ANDS     r2,r2,r3
000008  8002              STRH     r2,[r0,#0]
;;;551    
;;;552      /* Configure the OPM Mode */
;;;553      TIMx->CR1 |= TIM_OPMode;
00000a  8802              LDRH     r2,[r0,#0]
00000c  430a              ORRS     r2,r2,r1
00000e  8002              STRH     r2,[r0,#0]
;;;554    }
000010  4770              BX       lr
;;;555    
                          ENDP


                          AREA ||i.TIM_SelectOutputTrigger||, CODE, READONLY, ALIGN=1

                  TIM_SelectOutputTrigger PROC
;;;2921     */
;;;2922   void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
000000  8882              LDRH     r2,[r0,#4]
;;;2923   {
;;;2924     /* Check the parameters */
;;;2925     assert_param(IS_TIM_LIST5_PERIPH(TIMx));
;;;2926     assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
;;;2927   
;;;2928     /* Reset the MMS Bits */
;;;2929     TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
000002  f64f738f          MOV      r3,#0xff8f
000006  401a              ANDS     r2,r2,r3
000008  8082              STRH     r2,[r0,#4]
;;;2930     /* Select the TRGO source */
;;;2931     TIMx->CR2 |=  TIM_TRGOSource;
00000a  8882              LDRH     r2,[r0,#4]
00000c  430a              ORRS     r2,r2,r1
00000e  8082              STRH     r2,[r0,#4]
;;;2932   }
000010  4770              BX       lr
;;;2933   
                          ENDP


                          AREA ||i.TIM_SelectSlaveMode||, CODE, READONLY, ALIGN=1

                  TIM_SelectSlaveMode PROC
;;;2945     */
;;;2946   void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
000000  8902              LDRH     r2,[r0,#8]
;;;2947   {
;;;2948     /* Check the parameters */
;;;2949     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2950     assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
;;;2951   
;;;2952     /* Reset the SMS Bits */
;;;2953     TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
000002  f64f73f8          MOV      r3,#0xfff8
000006  401a              ANDS     r2,r2,r3
000008  8102              STRH     r2,[r0,#8]
;;;2954   
;;;2955     /* Select the Slave Mode */
;;;2956     TIMx->SMCR |= TIM_SlaveMode;
00000a  8902              LDRH     r2,[r0,#8]
00000c  430a              ORRS     r2,r2,r1
00000e  8102              STRH     r2,[r0,#8]
;;;2957   }
000010  4770              BX       lr
;;;2958   
                          ENDP


                          AREA ||i.TIM_SetAutoreload||, CODE, READONLY, ALIGN=1

                  TIM_SetAutoreload PROC
;;;417      */
;;;418    void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
000000  62c1              STR      r1,[r0,#0x2c]
;;;419    {
;;;420      /* Check the parameters */
;;;421      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;422      
;;;423      /* Set the Autoreload Register value */
;;;424      TIMx->ARR = Autoreload;
;;;425    }
000002  4770              BX       lr
;;;426    
                          ENDP


                          AREA ||i.TIM_SetClockDivision||, CODE, READONLY, ALIGN=1

                  TIM_SetClockDivision PROC
;;;565      */
;;;566    void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
000000  8802              LDRH     r2,[r0,#0]
;;;567    {
;;;568      /* Check the parameters */
;;;569      assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;570      assert_param(IS_TIM_CKD_DIV(TIM_CKD));
;;;571    
;;;572      /* Reset the CKD Bits */
;;;573      TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
000002  f64f43ff          MOV      r3,#0xfcff
000006  401a              ANDS     r2,r2,r3
000008  8002              STRH     r2,[r0,#0]
;;;574    
;;;575      /* Set the CKD value */
;;;576      TIMx->CR1 |= TIM_CKD;
00000a  8802              LDRH     r2,[r0,#0]
00000c  430a              ORRS     r2,r2,r1
00000e  8002              STRH     r2,[r0,#0]
;;;577    }
000010  4770              BX       lr
;;;578    
                          ENDP


                          AREA ||i.TIM_SetCompare1||, CODE, READONLY, ALIGN=1

                  TIM_SetCompare1 PROC
;;;1051     */
;;;1052   void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
000000  6341              STR      r1,[r0,#0x34]
;;;1053   {
;;;1054     /* Check the parameters */
;;;1055     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1056   
;;;1057     /* Set the Capture Compare1 Register value */
;;;1058     TIMx->CCR1 = Compare1;
;;;1059   }
000002  4770              BX       lr
;;;1060   
                          ENDP


                          AREA ||i.TIM_SetCompare2||, CODE, READONLY, ALIGN=1

                  TIM_SetCompare2 PROC
;;;1067     */
;;;1068   void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
000000  6381              STR      r1,[r0,#0x38]
;;;1069   {
;;;1070     /* Check the parameters */
;;;1071     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1072   
;;;1073     /* Set the Capture Compare2 Register value */
;;;1074     TIMx->CCR2 = Compare2;
;;;1075   }
000002  4770              BX       lr
;;;1076   
                          ENDP


                          AREA ||i.TIM_SetCompare3||, CODE, READONLY, ALIGN=1

                  TIM_SetCompare3 PROC
;;;1082     */
;;;1083   void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
000000  63c1              STR      r1,[r0,#0x3c]
;;;1084   {
;;;1085     /* Check the parameters */
;;;1086     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1087   
;;;1088     /* Set the Capture Compare3 Register value */
;;;1089     TIMx->CCR3 = Compare3;
;;;1090   }
000002  4770              BX       lr
;;;1091   
                          ENDP


                          AREA ||i.TIM_SetCompare4||, CODE, READONLY, ALIGN=1

                  TIM_SetCompare4 PROC
;;;1097     */
;;;1098   void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
000000  6401              STR      r1,[r0,#0x40]
;;;1099   {
;;;1100     /* Check the parameters */
;;;1101     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1102   
;;;1103     /* Set the Capture Compare4 Register value */
;;;1104     TIMx->CCR4 = Compare4;
;;;1105   }
000002  4770              BX       lr
;;;1106   
                          ENDP


                          AREA ||i.TIM_SetCounter||, CODE, READONLY, ALIGN=1

                  TIM_SetCounter PROC
;;;402      */
;;;403    void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
000000  6241              STR      r1,[r0,#0x24]
;;;404    {
;;;405      /* Check the parameters */
;;;406       assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;407    
;;;408      /* Set the Counter Register value */
;;;409      TIMx->CNT = Counter;
;;;410    }
000002  4770              BX       lr
;;;411    
                          ENDP


                          AREA ||i.TIM_SetIC1Prescaler||, CODE, READONLY, ALIGN=1

                  TIM_SetIC1Prescaler PROC
;;;2084     */
;;;2085   void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;2086   {
;;;2087     /* Check the parameters */
;;;2088     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;2089     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2090   
;;;2091     /* Reset the IC1PSC Bits */
;;;2092     TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;
000002  f64f73f3          MOV      r3,#0xfff3
000006  401a              ANDS     r2,r2,r3
000008  8302              STRH     r2,[r0,#0x18]
;;;2093   
;;;2094     /* Set the IC1PSC value */
;;;2095     TIMx->CCMR1 |= TIM_ICPSC;
00000a  8b02              LDRH     r2,[r0,#0x18]
00000c  430a              ORRS     r2,r2,r1
00000e  8302              STRH     r2,[r0,#0x18]
;;;2096   }
000010  4770              BX       lr
;;;2097   
                          ENDP


                          AREA ||i.TIM_SetIC2Prescaler||, CODE, READONLY, ALIGN=1

                  TIM_SetIC2Prescaler PROC
;;;2109     */
;;;2110   void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;2111   {
;;;2112     /* Check the parameters */
;;;2113     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2114     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2115   
;;;2116     /* Reset the IC2PSC Bits */
;;;2117     TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;
000002  f24f33ff          MOV      r3,#0xf3ff
000006  401a              ANDS     r2,r2,r3
000008  8302              STRH     r2,[r0,#0x18]
;;;2118   
;;;2119     /* Set the IC2PSC value */
;;;2120     TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
00000a  8b02              LDRH     r2,[r0,#0x18]
00000c  060b              LSLS     r3,r1,#24
00000e  ea424213          ORR      r2,r2,r3,LSR #16
000012  8302              STRH     r2,[r0,#0x18]
;;;2121   }
000014  4770              BX       lr
;;;2122   
                          ENDP


                          AREA ||i.TIM_SetIC3Prescaler||, CODE, READONLY, ALIGN=1

                  TIM_SetIC3Prescaler PROC
;;;2133     */
;;;2134   void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;2135   {
;;;2136     /* Check the parameters */
;;;2137     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2138     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2139   
;;;2140     /* Reset the IC3PSC Bits */
;;;2141     TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
000002  f64f73f3          MOV      r3,#0xfff3
000006  401a              ANDS     r2,r2,r3
000008  8382              STRH     r2,[r0,#0x1c]
;;;2142   
;;;2143     /* Set the IC3PSC value */
;;;2144     TIMx->CCMR2 |= TIM_ICPSC;
00000a  8b82              LDRH     r2,[r0,#0x1c]
00000c  430a              ORRS     r2,r2,r1
00000e  8382              STRH     r2,[r0,#0x1c]
;;;2145   }
000010  4770              BX       lr
;;;2146   
                          ENDP


                          AREA ||i.TIM_SetIC4Prescaler||, CODE, READONLY, ALIGN=1

                  TIM_SetIC4Prescaler PROC
;;;2157     */
;;;2158   void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;2159   {  
;;;2160     /* Check the parameters */
;;;2161     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2162     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2163   
;;;2164     /* Reset the IC4PSC Bits */
;;;2165     TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
000002  f24f33ff          MOV      r3,#0xf3ff
000006  401a              ANDS     r2,r2,r3
000008  8382              STRH     r2,[r0,#0x1c]
;;;2166   
;;;2167     /* Set the IC4PSC value */
;;;2168     TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
00000a  8b82              LDRH     r2,[r0,#0x1c]
00000c  060b              LSLS     r3,r1,#24
00000e  ea424213          ORR      r2,r2,r3,LSR #16
000012  8382              STRH     r2,[r0,#0x1c]
;;;2169   }
000014  4770              BX       lr
;;;2170   /**
                          ENDP


                          AREA ||i.TIM_TIxExternalClockConfig||, CODE, READONLY, ALIGN=1

                  TIM_TIxExternalClockConfig PROC
;;;2723     */
;;;2724   void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
000000  e92d41f0          PUSH     {r4-r8,lr}
;;;2725                                   uint16_t TIM_ICPolarity, uint16_t ICFilter)
;;;2726   {
000004  4604              MOV      r4,r0
000006  460d              MOV      r5,r1
000008  4616              MOV      r6,r2
00000a  461f              MOV      r7,r3
;;;2727     /* Check the parameters */
;;;2728     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;2729     assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
;;;2730     assert_param(IS_TIM_IC_FILTER(ICFilter));
;;;2731   
;;;2732     /* Configure the Timer Input Clock Source */
;;;2733     if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
00000c  2d60              CMP      r5,#0x60
00000e  d106              BNE      |L88.30|
;;;2734     {
;;;2735       TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
000010  463b              MOV      r3,r7
000012  2201              MOVS     r2,#1
000014  4631              MOV      r1,r6
000016  4620              MOV      r0,r4
000018  f7fffffe          BL       TI2_Config
00001c  e005              B        |L88.42|
                  |L88.30|
;;;2736     }
;;;2737     else
;;;2738     {
;;;2739       TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
00001e  463b              MOV      r3,r7
000020  2201              MOVS     r2,#1
000022  4631              MOV      r1,r6
000024  4620              MOV      r0,r4
000026  f7fffffe          BL       TI1_Config
                  |L88.42|
;;;2740     }
;;;2741     /* Select the Trigger source */
;;;2742     TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
00002a  4629              MOV      r1,r5
00002c  4620              MOV      r0,r4
00002e  f7fffffe          BL       TIM_SelectInputTrigger
;;;2743     /* Select the External clock mode1 */
;;;2744     TIMx->SMCR |= TIM_SlaveMode_External1;
000032  8920              LDRH     r0,[r4,#8]
000034  f0400007          ORR      r0,r0,#7
000038  8120              STRH     r0,[r4,#8]
;;;2745   }
00003a  e8bd81f0          POP      {r4-r8,pc}
;;;2746   
                          ENDP


                          AREA ||i.TIM_TimeBaseInit||, CODE, READONLY, ALIGN=2

                  TIM_TimeBaseInit PROC
;;;281      */
;;;282    void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
000000  2200              MOVS     r2,#0
;;;283    {
;;;284      uint16_t tmpcr1 = 0;
;;;285    
;;;286      /* Check the parameters */
;;;287      assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
;;;288      assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
;;;289      assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
;;;290    
;;;291      tmpcr1 = TIMx->CR1;  
000002  8802              LDRH     r2,[r0,#0]
;;;292    
;;;293      if((TIMx == TIM1) || (TIMx == TIM8)||
000004  4b18              LDR      r3,|L89.104|
000006  4298              CMP      r0,r3
000008  d00e              BEQ      |L89.40|
00000a  4b18              LDR      r3,|L89.108|
00000c  4298              CMP      r0,r3
00000e  d00b              BEQ      |L89.40|
;;;294         (TIMx == TIM2) || (TIMx == TIM3)||
000010  f1b04f80          CMP      r0,#0x40000000
000014  d008              BEQ      |L89.40|
000016  4b16              LDR      r3,|L89.112|
000018  4298              CMP      r0,r3
00001a  d005              BEQ      |L89.40|
;;;295         (TIMx == TIM4) || (TIMx == TIM5)) 
00001c  4b15              LDR      r3,|L89.116|
00001e  4298              CMP      r0,r3
000020  d002              BEQ      |L89.40|
000022  4b15              LDR      r3,|L89.120|
000024  4298              CMP      r0,r3
000026  d104              BNE      |L89.50|
                  |L89.40|
;;;296      {
;;;297        /* Select the Counter Mode */
;;;298        tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
000028  f64f738f          MOV      r3,#0xff8f
00002c  401a              ANDS     r2,r2,r3
;;;299        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
00002e  884b              LDRH     r3,[r1,#2]
000030  431a              ORRS     r2,r2,r3
                  |L89.50|
;;;300      }
;;;301     
;;;302      if((TIMx != TIM6) && (TIMx != TIM7))
000032  4b12              LDR      r3,|L89.124|
000034  4298              CMP      r0,r3
000036  d007              BEQ      |L89.72|
000038  4b11              LDR      r3,|L89.128|
00003a  4298              CMP      r0,r3
00003c  d004              BEQ      |L89.72|
;;;303      {
;;;304        /* Set the clock division */
;;;305        tmpcr1 &=  (uint16_t)(~TIM_CR1_CKD);
00003e  f64f43ff          MOV      r3,#0xfcff
000042  401a              ANDS     r2,r2,r3
;;;306        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
000044  890b              LDRH     r3,[r1,#8]
000046  431a              ORRS     r2,r2,r3
                  |L89.72|
;;;307      }
;;;308    
;;;309      TIMx->CR1 = tmpcr1;
000048  8002              STRH     r2,[r0,#0]
;;;310    
;;;311      /* Set the Autoreload value */
;;;312      TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
00004a  684b              LDR      r3,[r1,#4]
00004c  62c3              STR      r3,[r0,#0x2c]
;;;313     
;;;314      /* Set the Prescaler value */
;;;315      TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
00004e  880b              LDRH     r3,[r1,#0]
000050  8503              STRH     r3,[r0,#0x28]
;;;316        
;;;317      if ((TIMx == TIM1) || (TIMx == TIM8))  
000052  4b05              LDR      r3,|L89.104|
000054  4298              CMP      r0,r3
000056  d002              BEQ      |L89.94|
000058  4b04              LDR      r3,|L89.108|
00005a  4298              CMP      r0,r3
00005c  d101              BNE      |L89.98|
                  |L89.94|
;;;318      {
;;;319        /* Set the Repetition Counter value */
;;;320        TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
00005e  7a8b              LDRB     r3,[r1,#0xa]
000060  8603              STRH     r3,[r0,#0x30]
                  |L89.98|
;;;321      }
;;;322    
;;;323      /* Generate an update event to reload the Prescaler 
;;;324         and the repetition counter(only for TIM1 and TIM8) value immediatly */
;;;325      TIMx->EGR = TIM_PSCReloadMode_Immediate;          
000062  2301              MOVS     r3,#1
000064  8283              STRH     r3,[r0,#0x14]
;;;326    }
000066  4770              BX       lr
;;;327    
                          ENDP

                  |L89.104|
                          DCD      0x40010000
                  |L89.108|
                          DCD      0x40010400
                  |L89.112|
                          DCD      0x40000400
                  |L89.116|
                          DCD      0x40000800
                  |L89.120|
                          DCD      0x40000c00
                  |L89.124|
                          DCD      0x40001000
                  |L89.128|
                          DCD      0x40001400

                          AREA ||i.TIM_TimeBaseStructInit||, CODE, READONLY, ALIGN=1

                  TIM_TimeBaseStructInit PROC
;;;333      */
;;;334    void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
000000  f04f31ff          MOV      r1,#0xffffffff
;;;335    {
;;;336      /* Set the default configuration */
;;;337      TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
000004  6041              STR      r1,[r0,#4]
;;;338      TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
000006  2100              MOVS     r1,#0
000008  8001              STRH     r1,[r0,#0]
;;;339      TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
00000a  8101              STRH     r1,[r0,#8]
;;;340      TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
00000c  8041              STRH     r1,[r0,#2]
;;;341      TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
00000e  7281              STRB     r1,[r0,#0xa]
;;;342    }
000010  4770              BX       lr
;;;343    
                          ENDP


                          AREA ||i.TIM_UpdateDisableConfig||, CODE, READONLY, ALIGN=1

                  TIM_UpdateDisableConfig PROC
;;;461      */
;;;462    void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  b121              CBZ      r1,|L91.12|
;;;463    {
;;;464      /* Check the parameters */
;;;465      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;466      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;467    
;;;468      if (NewState != DISABLE)
;;;469      {
;;;470        /* Set the Update Disable Bit */
;;;471        TIMx->CR1 |= TIM_CR1_UDIS;
000002  8802              LDRH     r2,[r0,#0]
000004  f0420202          ORR      r2,r2,#2
000008  8002              STRH     r2,[r0,#0]
00000a  e004              B        |L91.22|
                  |L91.12|
;;;472      }
;;;473      else
;;;474      {
;;;475        /* Reset the Update Disable Bit */
;;;476        TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
00000c  8802              LDRH     r2,[r0,#0]
00000e  f64f73fd          MOV      r3,#0xfffd
000012  401a              ANDS     r2,r2,r3
000014  8002              STRH     r2,[r0,#0]
                  |L91.22|
;;;477      }
;;;478    }
000016  4770              BX       lr
;;;479    
                          ENDP


                          AREA ||i.TIM_UpdateRequestConfig||, CODE, READONLY, ALIGN=1

                  TIM_UpdateRequestConfig PROC
;;;490      */
;;;491    void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
000000  b121              CBZ      r1,|L92.12|
;;;492    {
;;;493      /* Check the parameters */
;;;494      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;495      assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
;;;496    
;;;497      if (TIM_UpdateSource != TIM_UpdateSource_Global)
;;;498      {
;;;499        /* Set the URS Bit */
;;;500        TIMx->CR1 |= TIM_CR1_URS;
000002  8802              LDRH     r2,[r0,#0]
000004  f0420204          ORR      r2,r2,#4
000008  8002              STRH     r2,[r0,#0]
00000a  e004              B        |L92.22|
                  |L92.12|
;;;501      }
;;;502      else
;;;503      {
;;;504        /* Reset the URS Bit */
;;;505        TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
00000c  8802              LDRH     r2,[r0,#0]
00000e  f64f73fb          MOV      r3,#0xfffb
000012  401a              ANDS     r2,r2,r3
000014  8002              STRH     r2,[r0,#0]
                  |L92.22|
;;;506      }
;;;507    }
000016  4770              BX       lr
;;;508    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_tim.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_stm32f4xx_tim_c_c458916b____REV16|
#line 114 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f4xx_tim_c_c458916b____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_stm32f4xx_tim_c_c458916b____REVSH|
#line 128
|__asm___15_stm32f4xx_tim_c_c458916b____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
