; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\STM324xG_EVAL\stm32f4xx_rcc.o --asm_dir=.\STM324xG_EVAL\ --list_dir=.\STM324xG_EVAL\ --depend=.\STM324xG_EVAL\stm32f4xx_rcc.d --cpu=Cortex-M4.fp --apcs=interwork -O0 -Otime -I..\ -I..\..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\..\Utilities\STM32_EVAL\Common -I..\..\..\Utilities\STM32_EVAL\STM3240_41_G_EVAL -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F4xx -D__MICROLIB -DUSE_STM324xG_EVAL -DSTM32F4XX -DUSE_STDPERIPH_DRIVER --omf_browse=.\STM324xG_EVAL\stm32f4xx_rcc.crf ..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rcc.c]
                          THUMB

                          AREA ||i.RCC_AHB1PeriphClockCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB1PeriphClockCmd PROC
;;;1084     */
;;;1085   void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L1.14|
;;;1086   {
;;;1087     /* Check the parameters */
;;;1088     assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
;;;1089   
;;;1090     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1091     if (NewState != DISABLE)
;;;1092     {
;;;1093       RCC->AHB1ENR |= RCC_AHB1Periph;
000002  4a06              LDR      r2,|L1.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L1.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L1.24|
                  |L1.14|
;;;1094     }
;;;1095     else
;;;1096     {
;;;1097       RCC->AHB1ENR &= ~RCC_AHB1Periph;
00000e  4a03              LDR      r2,|L1.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L1.28|
000016  601a              STR      r2,[r3,#0]
                  |L1.24|
;;;1098     }
;;;1099   }
000018  4770              BX       lr
;;;1100   
                          ENDP

00001a  0000              DCW      0x0000
                  |L1.28|
                          DCD      0x40023830

                          AREA ||i.RCC_AHB1PeriphClockLPModeCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB1PeriphClockLPModeCmd PROC
;;;1454     */
;;;1455   void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L2.14|
;;;1456   {
;;;1457     /* Check the parameters */
;;;1458     assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
;;;1459     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1460     if (NewState != DISABLE)
;;;1461     {
;;;1462       RCC->AHB1LPENR |= RCC_AHB1Periph;
000002  4a06              LDR      r2,|L2.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L2.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L2.24|
                  |L2.14|
;;;1463     }
;;;1464     else
;;;1465     {
;;;1466       RCC->AHB1LPENR &= ~RCC_AHB1Periph;
00000e  4a03              LDR      r2,|L2.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L2.28|
000016  601a              STR      r2,[r3,#0]
                  |L2.24|
;;;1467     }
;;;1468   }
000018  4770              BX       lr
;;;1469   
                          ENDP

00001a  0000              DCW      0x0000
                  |L2.28|
                          DCD      0x40023850

                          AREA ||i.RCC_AHB1PeriphResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB1PeriphResetCmd PROC
;;;1272     */
;;;1273   void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L3.14|
;;;1274   {
;;;1275     /* Check the parameters */
;;;1276     assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
;;;1277     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1278   
;;;1279     if (NewState != DISABLE)
;;;1280     {
;;;1281       RCC->AHB1RSTR |= RCC_AHB1Periph;
000002  4a06              LDR      r2,|L3.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L3.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L3.24|
                  |L3.14|
;;;1282     }
;;;1283     else
;;;1284     {
;;;1285       RCC->AHB1RSTR &= ~RCC_AHB1Periph;
00000e  4a03              LDR      r2,|L3.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L3.28|
000016  601a              STR      r2,[r3,#0]
                  |L3.24|
;;;1286     }
;;;1287   }
000018  4770              BX       lr
;;;1288   
                          ENDP

00001a  0000              DCW      0x0000
                  |L3.28|
                          DCD      0x40023810

                          AREA ||i.RCC_AHB2PeriphClockCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB2PeriphClockCmd PROC
;;;1116     */
;;;1117   void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L4.14|
;;;1118   {
;;;1119     /* Check the parameters */
;;;1120     assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
;;;1121     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1122   
;;;1123     if (NewState != DISABLE)
;;;1124     {
;;;1125       RCC->AHB2ENR |= RCC_AHB2Periph;
000002  4a06              LDR      r2,|L4.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L4.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L4.24|
                  |L4.14|
;;;1126     }
;;;1127     else
;;;1128     {
;;;1129       RCC->AHB2ENR &= ~RCC_AHB2Periph;
00000e  4a03              LDR      r2,|L4.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L4.28|
000016  601a              STR      r2,[r3,#0]
                  |L4.24|
;;;1130     }
;;;1131   }
000018  4770              BX       lr
;;;1132   
                          ENDP

00001a  0000              DCW      0x0000
                  |L4.28|
                          DCD      0x40023834

                          AREA ||i.RCC_AHB2PeriphClockLPModeCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB2PeriphClockLPModeCmd PROC
;;;1486     */
;;;1487   void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L5.14|
;;;1488   {
;;;1489     /* Check the parameters */
;;;1490     assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
;;;1491     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1492     if (NewState != DISABLE)
;;;1493     {
;;;1494       RCC->AHB2LPENR |= RCC_AHB2Periph;
000002  4a06              LDR      r2,|L5.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L5.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L5.24|
                  |L5.14|
;;;1495     }
;;;1496     else
;;;1497     {
;;;1498       RCC->AHB2LPENR &= ~RCC_AHB2Periph;
00000e  4a03              LDR      r2,|L5.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L5.28|
000016  601a              STR      r2,[r3,#0]
                  |L5.24|
;;;1499     }
;;;1500   }
000018  4770              BX       lr
;;;1501   
                          ENDP

00001a  0000              DCW      0x0000
                  |L5.28|
                          DCD      0x40023854

                          AREA ||i.RCC_AHB2PeriphResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB2PeriphResetCmd PROC
;;;1301     */
;;;1302   void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L6.14|
;;;1303   {
;;;1304     /* Check the parameters */
;;;1305     assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
;;;1306     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1307   
;;;1308     if (NewState != DISABLE)
;;;1309     {
;;;1310       RCC->AHB2RSTR |= RCC_AHB2Periph;
000002  4a06              LDR      r2,|L6.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L6.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L6.24|
                  |L6.14|
;;;1311     }
;;;1312     else
;;;1313     {
;;;1314       RCC->AHB2RSTR &= ~RCC_AHB2Periph;
00000e  4a03              LDR      r2,|L6.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L6.28|
000016  601a              STR      r2,[r3,#0]
                  |L6.24|
;;;1315     }
;;;1316   }
000018  4770              BX       lr
;;;1317   
                          ENDP

00001a  0000              DCW      0x0000
                  |L6.28|
                          DCD      0x40023814

                          AREA ||i.RCC_AHB3PeriphClockCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB3PeriphClockCmd PROC
;;;1143     */
;;;1144   void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L7.14|
;;;1145   {
;;;1146     /* Check the parameters */
;;;1147     assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));  
;;;1148     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1149   
;;;1150     if (NewState != DISABLE)
;;;1151     {
;;;1152       RCC->AHB3ENR |= RCC_AHB3Periph;
000002  4a06              LDR      r2,|L7.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L7.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L7.24|
                  |L7.14|
;;;1153     }
;;;1154     else
;;;1155     {
;;;1156       RCC->AHB3ENR &= ~RCC_AHB3Periph;
00000e  4a03              LDR      r2,|L7.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L7.28|
000016  601a              STR      r2,[r3,#0]
                  |L7.24|
;;;1157     }
;;;1158   }
000018  4770              BX       lr
;;;1159   
                          ENDP

00001a  0000              DCW      0x0000
                  |L7.28|
                          DCD      0x40023838

                          AREA ||i.RCC_AHB3PeriphClockLPModeCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB3PeriphClockLPModeCmd PROC
;;;1513     */
;;;1514   void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L8.14|
;;;1515   {
;;;1516     /* Check the parameters */
;;;1517     assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
;;;1518     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1519     if (NewState != DISABLE)
;;;1520     {
;;;1521       RCC->AHB3LPENR |= RCC_AHB3Periph;
000002  4a06              LDR      r2,|L8.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L8.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L8.24|
                  |L8.14|
;;;1522     }
;;;1523     else
;;;1524     {
;;;1525       RCC->AHB3LPENR &= ~RCC_AHB3Periph;
00000e  4a03              LDR      r2,|L8.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L8.28|
000016  601a              STR      r2,[r3,#0]
                  |L8.24|
;;;1526     }
;;;1527   }
000018  4770              BX       lr
;;;1528   
                          ENDP

00001a  0000              DCW      0x0000
                  |L8.28|
                          DCD      0x40023858

                          AREA ||i.RCC_AHB3PeriphResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB3PeriphResetCmd PROC
;;;1325     */
;;;1326   void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L9.14|
;;;1327   {
;;;1328     /* Check the parameters */
;;;1329     assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
;;;1330     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1331   
;;;1332     if (NewState != DISABLE)
;;;1333     {
;;;1334       RCC->AHB3RSTR |= RCC_AHB3Periph;
000002  4a06              LDR      r2,|L9.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L9.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L9.24|
                  |L9.14|
;;;1335     }
;;;1336     else
;;;1337     {
;;;1338       RCC->AHB3RSTR &= ~RCC_AHB3Periph;
00000e  4a03              LDR      r2,|L9.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L9.28|
000016  601a              STR      r2,[r3,#0]
                  |L9.24|
;;;1339     }
;;;1340   }
000018  4770              BX       lr
;;;1341   
                          ENDP

00001a  0000              DCW      0x0000
                  |L9.28|
                          DCD      0x40023818

                          AREA ||i.RCC_APB1PeriphClockCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB1PeriphClockCmd PROC
;;;1193     */
;;;1194   void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L10.14|
;;;1195   {
;;;1196     /* Check the parameters */
;;;1197     assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));  
;;;1198     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1199   
;;;1200     if (NewState != DISABLE)
;;;1201     {
;;;1202       RCC->APB1ENR |= RCC_APB1Periph;
000002  4a06              LDR      r2,|L10.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L10.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L10.24|
                  |L10.14|
;;;1203     }
;;;1204     else
;;;1205     {
;;;1206       RCC->APB1ENR &= ~RCC_APB1Periph;
00000e  4a03              LDR      r2,|L10.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L10.28|
000016  601a              STR      r2,[r3,#0]
                  |L10.24|
;;;1207     }
;;;1208   }
000018  4770              BX       lr
;;;1209   
                          ENDP

00001a  0000              DCW      0x0000
                  |L10.28|
                          DCD      0x40023840

                          AREA ||i.RCC_APB1PeriphClockLPModeCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB1PeriphClockLPModeCmd PROC
;;;1563     */
;;;1564   void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L11.14|
;;;1565   {
;;;1566     /* Check the parameters */
;;;1567     assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;1568     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1569     if (NewState != DISABLE)
;;;1570     {
;;;1571       RCC->APB1LPENR |= RCC_APB1Periph;
000002  4a06              LDR      r2,|L11.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L11.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L11.24|
                  |L11.14|
;;;1572     }
;;;1573     else
;;;1574     {
;;;1575       RCC->APB1LPENR &= ~RCC_APB1Periph;
00000e  4a03              LDR      r2,|L11.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L11.28|
000016  601a              STR      r2,[r3,#0]
                  |L11.24|
;;;1576     }
;;;1577   }
000018  4770              BX       lr
;;;1578   
                          ENDP

00001a  0000              DCW      0x0000
                  |L11.28|
                          DCD      0x40023860

                          AREA ||i.RCC_APB1PeriphResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB1PeriphResetCmd PROC
;;;1372     */
;;;1373   void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L12.14|
;;;1374   {
;;;1375     /* Check the parameters */
;;;1376     assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;1377     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1378     if (NewState != DISABLE)
;;;1379     {
;;;1380       RCC->APB1RSTR |= RCC_APB1Periph;
000002  4a06              LDR      r2,|L12.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L12.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L12.24|
                  |L12.14|
;;;1381     }
;;;1382     else
;;;1383     {
;;;1384       RCC->APB1RSTR &= ~RCC_APB1Periph;
00000e  4a03              LDR      r2,|L12.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L12.28|
000016  601a              STR      r2,[r3,#0]
                  |L12.24|
;;;1385     }
;;;1386   }
000018  4770              BX       lr
;;;1387   
                          ENDP

00001a  0000              DCW      0x0000
                  |L12.28|
                          DCD      0x40023820

                          AREA ||i.RCC_APB2PeriphClockCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB2PeriphClockCmd PROC
;;;1233     */
;;;1234   void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L13.14|
;;;1235   {
;;;1236     /* Check the parameters */
;;;1237     assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;1238     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1239   
;;;1240     if (NewState != DISABLE)
;;;1241     {
;;;1242       RCC->APB2ENR |= RCC_APB2Periph;
000002  4a06              LDR      r2,|L13.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L13.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L13.24|
                  |L13.14|
;;;1243     }
;;;1244     else
;;;1245     {
;;;1246       RCC->APB2ENR &= ~RCC_APB2Periph;
00000e  4a03              LDR      r2,|L13.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L13.28|
000016  601a              STR      r2,[r3,#0]
                  |L13.24|
;;;1247     }
;;;1248   }
000018  4770              BX       lr
;;;1249   
                          ENDP

00001a  0000              DCW      0x0000
                  |L13.28|
                          DCD      0x40023844

                          AREA ||i.RCC_APB2PeriphClockLPModeCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB2PeriphClockLPModeCmd PROC
;;;1603     */
;;;1604   void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L14.14|
;;;1605   {
;;;1606     /* Check the parameters */
;;;1607     assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;1608     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1609     if (NewState != DISABLE)
;;;1610     {
;;;1611       RCC->APB2LPENR |= RCC_APB2Periph;
000002  4a06              LDR      r2,|L14.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L14.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L14.24|
                  |L14.14|
;;;1612     }
;;;1613     else
;;;1614     {
;;;1615       RCC->APB2LPENR &= ~RCC_APB2Periph;
00000e  4a03              LDR      r2,|L14.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L14.28|
000016  601a              STR      r2,[r3,#0]
                  |L14.24|
;;;1616     }
;;;1617   }
000018  4770              BX       lr
;;;1618   
                          ENDP

00001a  0000              DCW      0x0000
                  |L14.28|
                          DCD      0x40023864

                          AREA ||i.RCC_APB2PeriphResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB2PeriphResetCmd PROC
;;;1408     */
;;;1409   void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
000000  b129              CBZ      r1,|L15.14|
;;;1410   {
;;;1411     /* Check the parameters */
;;;1412     assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
;;;1413     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1414     if (NewState != DISABLE)
;;;1415     {
;;;1416       RCC->APB2RSTR |= RCC_APB2Periph;
000002  4a06              LDR      r2,|L15.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L15.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L15.24|
                  |L15.14|
;;;1417     }
;;;1418     else
;;;1419     {
;;;1420       RCC->APB2RSTR &= ~RCC_APB2Periph;
00000e  4a03              LDR      r2,|L15.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L15.28|
000016  601a              STR      r2,[r3,#0]
                  |L15.24|
;;;1421     }
;;;1422   }
000018  4770              BX       lr
;;;1423   
                          ENDP

00001a  0000              DCW      0x0000
                  |L15.28|
                          DCD      0x40023824

                          AREA ||i.RCC_AdjustHSICalibrationValue||, CODE, READONLY, ALIGN=2

                  RCC_AdjustHSICalibrationValue PROC
;;;291      */
;;;292    void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
000000  4601              MOV      r1,r0
;;;293    {
;;;294      uint32_t tmpreg = 0;
000002  2000              MOVS     r0,#0
;;;295      /* Check the parameters */
;;;296      assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
;;;297    
;;;298      tmpreg = RCC->CR;
000004  4a03              LDR      r2,|L16.20|
000006  6810              LDR      r0,[r2,#0]
;;;299    
;;;300      /* Clear HSITRIM[4:0] bits */
;;;301      tmpreg &= ~RCC_CR_HSITRIM;
000008  f02000f8          BIC      r0,r0,#0xf8
;;;302    
;;;303      /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
;;;304      tmpreg |= (uint32_t)HSICalibrationValue << 3;
00000c  ea4000c1          ORR      r0,r0,r1,LSL #3
;;;305    
;;;306      /* Store the new value */
;;;307      RCC->CR = tmpreg;
000010  6010              STR      r0,[r2,#0]
;;;308    }
000012  4770              BX       lr
;;;309    
                          ENDP

                  |L16.20|
                          DCD      0x40023800

                          AREA ||i.RCC_BackupResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_BackupResetCmd PROC
;;;1028     */
;;;1029   void RCC_BackupResetCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L17.8|
;;;1030   {
;;;1031     /* Check the parameters */
;;;1032     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1033     *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;1034   }
000004  4770              BX       lr
;;;1035   
                          ENDP

000006  0000              DCW      0x0000
                  |L17.8|
                          DCD      0x42470e40

                          AREA ||i.RCC_ClearFlag||, CODE, READONLY, ALIGN=2

                  RCC_ClearFlag PROC
;;;1729     */
;;;1730   void RCC_ClearFlag(void)
000000  4803              LDR      r0,|L18.16|
;;;1731   {
;;;1732     /* Set RMVF bit to clear the reset flags */
;;;1733     RCC->CSR |= RCC_CSR_RMVF;
000002  6800              LDR      r0,[r0,#0]
000004  f0407080          ORR      r0,r0,#0x1000000
000008  4901              LDR      r1,|L18.16|
00000a  6008              STR      r0,[r1,#0]
;;;1734   }
00000c  4770              BX       lr
;;;1735   
                          ENDP

00000e  0000              DCW      0x0000
                  |L18.16|
                          DCD      0x40023874

                          AREA ||i.RCC_ClearITPendingBit||, CODE, READONLY, ALIGN=2

                  RCC_ClearITPendingBit PROC
;;;1781     */
;;;1782   void RCC_ClearITPendingBit(uint8_t RCC_IT)
000000  4901              LDR      r1,|L19.8|
;;;1783   {
;;;1784     /* Check the parameters */
;;;1785     assert_param(IS_RCC_CLEAR_IT(RCC_IT));
;;;1786   
;;;1787     /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
;;;1788        pending bits */
;;;1789     *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
000002  7008              STRB     r0,[r1,#0]
;;;1790   }
000004  4770              BX       lr
;;;1791   
                          ENDP

000006  0000              DCW      0x0000
                  |L19.8|
                          DCD      0x4002380e

                          AREA ||i.RCC_ClockSecuritySystemCmd||, CODE, READONLY, ALIGN=2

                  RCC_ClockSecuritySystemCmd PROC
;;;517      */
;;;518    void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L20.8|
;;;519    {
;;;520      /* Check the parameters */
;;;521      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;522      *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
000002  64c8              STR      r0,[r1,#0x4c]
;;;523    }
000004  4770              BX       lr
;;;524    
                          ENDP

000006  0000              DCW      0x0000
                  |L20.8|
                          DCD      0x42470000

                          AREA ||i.RCC_DeInit||, CODE, READONLY, ALIGN=2

                  RCC_DeInit PROC
;;;195      */
;;;196    void RCC_DeInit(void)
000000  480e              LDR      r0,|L21.60|
;;;197    {
;;;198      /* Set HSION bit */
;;;199      RCC->CR |= (uint32_t)0x00000001;
000002  6800              LDR      r0,[r0,#0]
000004  f0400001          ORR      r0,r0,#1
000008  490c              LDR      r1,|L21.60|
00000a  6008              STR      r0,[r1,#0]
;;;200    
;;;201      /* Reset CFGR register */
;;;202      RCC->CFGR = 0x00000000;
00000c  2000              MOVS     r0,#0
00000e  490b              LDR      r1,|L21.60|
000010  3108              ADDS     r1,r1,#8
000012  6008              STR      r0,[r1,#0]
;;;203    
;;;204      /* Reset HSEON, CSSON and PLLON bits */
;;;205      RCC->CR &= (uint32_t)0xFEF6FFFF;
000014  4809              LDR      r0,|L21.60|
000016  6800              LDR      r0,[r0,#0]
000018  4909              LDR      r1,|L21.64|
00001a  4008              ANDS     r0,r0,r1
00001c  4907              LDR      r1,|L21.60|
00001e  6008              STR      r0,[r1,#0]
;;;206    
;;;207      /* Reset PLLCFGR register */
;;;208      RCC->PLLCFGR = 0x24003010;
000020  4808              LDR      r0,|L21.68|
000022  1d09              ADDS     r1,r1,#4
000024  6008              STR      r0,[r1,#0]
;;;209    
;;;210      /* Reset HSEBYP bit */
;;;211      RCC->CR &= (uint32_t)0xFFFBFFFF;
000026  1f08              SUBS     r0,r1,#4
000028  6800              LDR      r0,[r0,#0]
00002a  f4202080          BIC      r0,r0,#0x40000
00002e  1f09              SUBS     r1,r1,#4
000030  6008              STR      r0,[r1,#0]
;;;212    
;;;213      /* Disable all interrupts */
;;;214      RCC->CIR = 0x00000000;
000032  2000              MOVS     r0,#0
000034  4901              LDR      r1,|L21.60|
000036  310c              ADDS     r1,r1,#0xc
000038  6008              STR      r0,[r1,#0]
;;;215    }
00003a  4770              BX       lr
;;;216    
                          ENDP

                  |L21.60|
                          DCD      0x40023800
                  |L21.64|
                          DCD      0xfef6ffff
                  |L21.68|
                          DCD      0x24003010

                          AREA ||i.RCC_GetClocksFreq||, CODE, READONLY, ALIGN=2

                  RCC_GetClocksFreq PROC
;;;854      */
;;;855    void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
000000  b5f0              PUSH     {r4-r7,lr}
;;;856    {
;;;857      uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
000002  2100              MOVS     r1,#0
000004  2200              MOVS     r2,#0
000006  2400              MOVS     r4,#0
000008  2502              MOVS     r5,#2
00000a  468c              MOV      r12,r1
00000c  2302              MOVS     r3,#2
;;;858    
;;;859      /* Get SYSCLK source -------------------------------------------------------*/
;;;860      tmp = RCC->CFGR & RCC_CFGR_SWS;
00000e  4e30              LDR      r6,|L22.208|
000010  6836              LDR      r6,[r6,#0]
000012  f006010c          AND      r1,r6,#0xc
;;;861    
;;;862      switch (tmp)
000016  b121              CBZ      r1,|L22.34|
000018  2904              CMP      r1,#4
00001a  d005              BEQ      |L22.40|
00001c  2908              CMP      r1,#8
00001e  d133              BNE      |L22.136|
000020  e005              B        |L22.46|
                  |L22.34|
;;;863      {
;;;864        case 0x00:  /* HSI used as system clock source */
;;;865          RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
000022  4e2c              LDR      r6,|L22.212|
000024  6006              STR      r6,[r0,#0]
;;;866          break;
000026  e032              B        |L22.142|
                  |L22.40|
;;;867        case 0x04:  /* HSE used as system clock  source */
;;;868          RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
000028  4e2b              LDR      r6,|L22.216|
00002a  6006              STR      r6,[r0,#0]
;;;869          break;
00002c  e02f              B        |L22.142|
                  |L22.46|
;;;870        case 0x08:  /* PLL used as system clock  source */
;;;871    
;;;872          /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
;;;873             SYSCLK = PLL_VCO / PLLP
;;;874             */    
;;;875          pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
00002e  4e28              LDR      r6,|L22.208|
000030  1f36              SUBS     r6,r6,#4
000032  6836              LDR      r6,[r6,#0]
000034  f3c65c80          UBFX     r12,r6,#22,#1
;;;876          pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
000038  4e25              LDR      r6,|L22.208|
00003a  1f36              SUBS     r6,r6,#4
00003c  6836              LDR      r6,[r6,#0]
00003e  f006033f          AND      r3,r6,#0x3f
;;;877          
;;;878          if (pllsource != 0)
000042  f1bc0f00          CMP      r12,#0
000046  d00a              BEQ      |L22.94|
;;;879          {
;;;880            /* HSE used as PLL clock source */
;;;881            pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
000048  4e23              LDR      r6,|L22.216|
00004a  fbb6f6f3          UDIV     r6,r6,r3
00004e  4f20              LDR      r7,|L22.208|
000050  1f3f              SUBS     r7,r7,#4
000052  683f              LDR      r7,[r7,#0]
000054  f3c71788          UBFX     r7,r7,#6,#9
000058  fb06f407          MUL      r4,r6,r7
00005c  e009              B        |L22.114|
                  |L22.94|
;;;882          }
;;;883          else
;;;884          {
;;;885            /* HSI used as PLL clock source */
;;;886            pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
00005e  4e1d              LDR      r6,|L22.212|
000060  fbb6f6f3          UDIV     r6,r6,r3
000064  4f1a              LDR      r7,|L22.208|
000066  1f3f              SUBS     r7,r7,#4
000068  683f              LDR      r7,[r7,#0]
00006a  f3c71788          UBFX     r7,r7,#6,#9
00006e  fb06f407          MUL      r4,r6,r7
                  |L22.114|
;;;887          }
;;;888    
;;;889          pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
000072  4e17              LDR      r6,|L22.208|
000074  1f36              SUBS     r6,r6,#4
000076  6836              LDR      r6,[r6,#0]
000078  f3c64601          UBFX     r6,r6,#16,#2
00007c  1c76              ADDS     r6,r6,#1
00007e  0075              LSLS     r5,r6,#1
;;;890          RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
000080  fbb4f6f5          UDIV     r6,r4,r5
000084  6006              STR      r6,[r0,#0]
;;;891          break;
000086  e002              B        |L22.142|
                  |L22.136|
;;;892        default:
;;;893          RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
000088  4e12              LDR      r6,|L22.212|
00008a  6006              STR      r6,[r0,#0]
;;;894          break;
00008c  bf00              NOP      
                  |L22.142|
00008e  bf00              NOP                            ;866
;;;895      }
;;;896      /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
;;;897    
;;;898      /* Get HCLK prescaler */
;;;899      tmp = RCC->CFGR & RCC_CFGR_HPRE;
000090  4e0f              LDR      r6,|L22.208|
000092  6836              LDR      r6,[r6,#0]
000094  f00601f0          AND      r1,r6,#0xf0
;;;900      tmp = tmp >> 4;
000098  0909              LSRS     r1,r1,#4
;;;901      presc = APBAHBPrescTable[tmp];
00009a  4e10              LDR      r6,|L22.220|
00009c  5c72              LDRB     r2,[r6,r1]
;;;902      /* HCLK clock frequency */
;;;903      RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
00009e  6806              LDR      r6,[r0,#0]
0000a0  40d6              LSRS     r6,r6,r2
0000a2  6046              STR      r6,[r0,#4]
;;;904    
;;;905      /* Get PCLK1 prescaler */
;;;906      tmp = RCC->CFGR & RCC_CFGR_PPRE1;
0000a4  4e0a              LDR      r6,|L22.208|
0000a6  6836              LDR      r6,[r6,#0]
0000a8  f40651e0          AND      r1,r6,#0x1c00
;;;907      tmp = tmp >> 10;
0000ac  0a89              LSRS     r1,r1,#10
;;;908      presc = APBAHBPrescTable[tmp];
0000ae  4e0b              LDR      r6,|L22.220|
0000b0  5c72              LDRB     r2,[r6,r1]
;;;909      /* PCLK1 clock frequency */
;;;910      RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
0000b2  6846              LDR      r6,[r0,#4]
0000b4  40d6              LSRS     r6,r6,r2
0000b6  6086              STR      r6,[r0,#8]
;;;911    
;;;912      /* Get PCLK2 prescaler */
;;;913      tmp = RCC->CFGR & RCC_CFGR_PPRE2;
0000b8  4e05              LDR      r6,|L22.208|
0000ba  6836              LDR      r6,[r6,#0]
0000bc  f4064160          AND      r1,r6,#0xe000
;;;914      tmp = tmp >> 13;
0000c0  0b49              LSRS     r1,r1,#13
;;;915      presc = APBAHBPrescTable[tmp];
0000c2  4e06              LDR      r6,|L22.220|
0000c4  5c72              LDRB     r2,[r6,r1]
;;;916      /* PCLK2 clock frequency */
;;;917      RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
0000c6  6846              LDR      r6,[r0,#4]
0000c8  40d6              LSRS     r6,r6,r2
0000ca  60c6              STR      r6,[r0,#0xc]
;;;918    }
0000cc  bdf0              POP      {r4-r7,pc}
;;;919    
                          ENDP

0000ce  0000              DCW      0x0000
                  |L22.208|
                          DCD      0x40023808
                  |L22.212|
                          DCD      0x00f42400
                  |L22.216|
                          DCD      0x017d7840
                  |L22.220|
                          DCD      APBAHBPrescTable

                          AREA ||i.RCC_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  RCC_GetFlagStatus PROC
;;;1684     */
;;;1685   FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
000000  b510              PUSH     {r4,lr}
;;;1686   {
000002  4601              MOV      r1,r0
;;;1687     uint32_t tmp = 0;
000004  2200              MOVS     r2,#0
;;;1688     uint32_t statusreg = 0;
000006  2300              MOVS     r3,#0
;;;1689     FlagStatus bitstatus = RESET;
000008  2000              MOVS     r0,#0
;;;1690   
;;;1691     /* Check the parameters */
;;;1692     assert_param(IS_RCC_FLAG(RCC_FLAG));
;;;1693   
;;;1694     /* Get the RCC register index */
;;;1695     tmp = RCC_FLAG >> 5;
00000a  114a              ASRS     r2,r1,#5
;;;1696     if (tmp == 1)               /* The flag to check is in CR register */
00000c  2a01              CMP      r2,#1
00000e  d102              BNE      |L23.22|
;;;1697     {
;;;1698       statusreg = RCC->CR;
000010  4c0a              LDR      r4,|L23.60|
000012  6823              LDR      r3,[r4,#0]
000014  e008              B        |L23.40|
                  |L23.22|
;;;1699     }
;;;1700     else if (tmp == 2)          /* The flag to check is in BDCR register */
000016  2a02              CMP      r2,#2
000018  d103              BNE      |L23.34|
;;;1701     {
;;;1702       statusreg = RCC->BDCR;
00001a  4c08              LDR      r4,|L23.60|
00001c  3470              ADDS     r4,r4,#0x70
00001e  6823              LDR      r3,[r4,#0]
000020  e002              B        |L23.40|
                  |L23.34|
;;;1703     }
;;;1704     else                       /* The flag to check is in CSR register */
;;;1705     {
;;;1706       statusreg = RCC->CSR;
000022  4c06              LDR      r4,|L23.60|
000024  3474              ADDS     r4,r4,#0x74
000026  6823              LDR      r3,[r4,#0]
                  |L23.40|
;;;1707     }
;;;1708   
;;;1709     /* Get the flag position */
;;;1710     tmp = RCC_FLAG & FLAG_MASK;
000028  f001021f          AND      r2,r1,#0x1f
;;;1711     if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
00002c  2401              MOVS     r4,#1
00002e  4094              LSLS     r4,r4,r2
000030  421c              TST      r4,r3
000032  d001              BEQ      |L23.56|
;;;1712     {
;;;1713       bitstatus = SET;
000034  2001              MOVS     r0,#1
000036  e000              B        |L23.58|
                  |L23.56|
;;;1714     }
;;;1715     else
;;;1716     {
;;;1717       bitstatus = RESET;
000038  2000              MOVS     r0,#0
                  |L23.58|
;;;1718     }
;;;1719     /* Return the flag status */
;;;1720     return bitstatus;
;;;1721   }
00003a  bd10              POP      {r4,pc}
;;;1722   
                          ENDP

                  |L23.60|
                          DCD      0x40023800

                          AREA ||i.RCC_GetITStatus||, CODE, READONLY, ALIGN=2

                  RCC_GetITStatus PROC
;;;1748     */
;;;1749   ITStatus RCC_GetITStatus(uint8_t RCC_IT)
000000  4601              MOV      r1,r0
;;;1750   {
;;;1751     ITStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;1752   
;;;1753     /* Check the parameters */
;;;1754     assert_param(IS_RCC_GET_IT(RCC_IT));
;;;1755   
;;;1756     /* Check the status of the specified RCC interrupt */
;;;1757     if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
000004  4a03              LDR      r2,|L24.20|
000006  6812              LDR      r2,[r2,#0]
000008  420a              TST      r2,r1
00000a  d001              BEQ      |L24.16|
;;;1758     {
;;;1759       bitstatus = SET;
00000c  2001              MOVS     r0,#1
00000e  e000              B        |L24.18|
                  |L24.16|
;;;1760     }
;;;1761     else
;;;1762     {
;;;1763       bitstatus = RESET;
000010  2000              MOVS     r0,#0
                  |L24.18|
;;;1764     }
;;;1765     /* Return the RCC_IT status */
;;;1766     return  bitstatus;
;;;1767   }
000012  4770              BX       lr
;;;1768   
                          ENDP

                  |L24.20|
                          DCD      0x4002380c

                          AREA ||i.RCC_GetSYSCLKSource||, CODE, READONLY, ALIGN=2

                  RCC_GetSYSCLKSource PROC
;;;714      */
;;;715    uint8_t RCC_GetSYSCLKSource(void)
000000  4802              LDR      r0,|L25.12|
;;;716    {
;;;717      return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
000002  6800              LDR      r0,[r0,#0]
000004  f000000c          AND      r0,r0,#0xc
;;;718    }
000008  4770              BX       lr
;;;719    
                          ENDP

00000a  0000              DCW      0x0000
                  |L25.12|
                          DCD      0x40023808

                          AREA ||i.RCC_HCLKConfig||, CODE, READONLY, ALIGN=2

                  RCC_HCLKConfig PROC
;;;739      */
;;;740    void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
000000  4601              MOV      r1,r0
;;;741    {
;;;742      uint32_t tmpreg = 0;
000002  2000              MOVS     r0,#0
;;;743      
;;;744      /* Check the parameters */
;;;745      assert_param(IS_RCC_HCLK(RCC_SYSCLK));
;;;746    
;;;747      tmpreg = RCC->CFGR;
000004  4a03              LDR      r2,|L26.20|
000006  6810              LDR      r0,[r2,#0]
;;;748    
;;;749      /* Clear HPRE[3:0] bits */
;;;750      tmpreg &= ~RCC_CFGR_HPRE;
000008  f02000f0          BIC      r0,r0,#0xf0
;;;751    
;;;752      /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
;;;753      tmpreg |= RCC_SYSCLK;
00000c  4308              ORRS     r0,r0,r1
;;;754    
;;;755      /* Store the new value */
;;;756      RCC->CFGR = tmpreg;
00000e  6010              STR      r0,[r2,#0]
;;;757    }
000010  4770              BX       lr
;;;758    
                          ENDP

000012  0000              DCW      0x0000
                  |L26.20|
                          DCD      0x40023808

                          AREA ||i.RCC_HSEConfig||, CODE, READONLY, ALIGN=2

                  RCC_HSEConfig PROC
;;;236      */
;;;237    void RCC_HSEConfig(uint8_t RCC_HSE)
000000  2100              MOVS     r1,#0
;;;238    {
;;;239      /* Check the parameters */
;;;240      assert_param(IS_RCC_HSE(RCC_HSE));
;;;241    
;;;242      /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
;;;243      *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
000002  4a02              LDR      r2,|L27.12|
000004  7011              STRB     r1,[r2,#0]
;;;244    
;;;245      /* Set the new HSE configuration -------------------------------------------*/
;;;246      *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
000006  4611              MOV      r1,r2
000008  7008              STRB     r0,[r1,#0]
;;;247    }
00000a  4770              BX       lr
;;;248    
                          ENDP

                  |L27.12|
                          DCD      0x40023802

                          AREA ||i.RCC_HSICmd||, CODE, READONLY, ALIGN=2

                  RCC_HSICmd PROC
;;;327      */
;;;328    void RCC_HSICmd(FunctionalState NewState)
000000  4901              LDR      r1,|L28.8|
;;;329    {
;;;330      /* Check the parameters */
;;;331      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;332    
;;;333      *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;334    }
000004  4770              BX       lr
;;;335    
                          ENDP

000006  0000              DCW      0x0000
                  |L28.8|
                          DCD      0x42470000

                          AREA ||i.RCC_I2SCLKConfig||, CODE, READONLY, ALIGN=2

                  RCC_I2SCLKConfig PROC
;;;1045     */
;;;1046   void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
000000  4901              LDR      r1,|L29.8|
;;;1047   {
;;;1048     /* Check the parameters */
;;;1049     assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
;;;1050   
;;;1051     *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
000002  6008              STR      r0,[r1,#0]
;;;1052   }
000004  4770              BX       lr
;;;1053   
                          ENDP

000006  0000              DCW      0x0000
                  |L29.8|
                          DCD      0x4247015c

                          AREA ||i.RCC_ITConfig||, CODE, READONLY, ALIGN=2

                  RCC_ITConfig PROC
;;;1648     */
;;;1649   void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
000000  b129              CBZ      r1,|L30.14|
;;;1650   {
;;;1651     /* Check the parameters */
;;;1652     assert_param(IS_RCC_IT(RCC_IT));
;;;1653     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1654     if (NewState != DISABLE)
;;;1655     {
;;;1656       /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
;;;1657       *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
000002  4a07              LDR      r2,|L30.32|
000004  7812              LDRB     r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b05              LDR      r3,|L30.32|
00000a  701a              STRB     r2,[r3,#0]
00000c  e006              B        |L30.28|
                  |L30.14|
;;;1658     }
;;;1659     else
;;;1660     {
;;;1661       /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
;;;1662       *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
00000e  4a04              LDR      r2,|L30.32|
000010  7812              LDRB     r2,[r2,#0]
000012  43c3              MVNS     r3,r0
000014  b2db              UXTB     r3,r3
000016  401a              ANDS     r2,r2,r3
000018  4b01              LDR      r3,|L30.32|
00001a  701a              STRB     r2,[r3,#0]
                  |L30.28|
;;;1663     }
;;;1664   }
00001c  4770              BX       lr
;;;1665   
                          ENDP

00001e  0000              DCW      0x0000
                  |L30.32|
                          DCD      0x4002380d

                          AREA ||i.RCC_LSEConfig||, CODE, READONLY, ALIGN=2

                  RCC_LSEConfig PROC
;;;352      */
;;;353    void RCC_LSEConfig(uint8_t RCC_LSE)
000000  2100              MOVS     r1,#0
;;;354    {
;;;355      /* Check the parameters */
;;;356      assert_param(IS_RCC_LSE(RCC_LSE));
;;;357    
;;;358      /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
;;;359      /* Reset LSEON bit */
;;;360      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
000002  4a09              LDR      r2,|L31.40|
000004  7011              STRB     r1,[r2,#0]
;;;361    
;;;362      /* Reset LSEBYP bit */
;;;363      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
000006  7011              STRB     r1,[r2,#0]
;;;364    
;;;365      /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;366      switch (RCC_LSE)
000008  2801              CMP      r0,#1
00000a  d002              BEQ      |L31.18|
00000c  2804              CMP      r0,#4
00000e  d108              BNE      |L31.34|
000010  e003              B        |L31.26|
                  |L31.18|
;;;367      {
;;;368        case RCC_LSE_ON:
;;;369          /* Set LSEON bit */
;;;370          *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
000012  2101              MOVS     r1,#1
000014  4a04              LDR      r2,|L31.40|
000016  7011              STRB     r1,[r2,#0]
;;;371          break;
000018  e004              B        |L31.36|
                  |L31.26|
;;;372        case RCC_LSE_Bypass:
;;;373          /* Set LSEBYP and LSEON bits */
;;;374          *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
00001a  2105              MOVS     r1,#5
00001c  4a02              LDR      r2,|L31.40|
00001e  7011              STRB     r1,[r2,#0]
;;;375          break;
000020  e000              B        |L31.36|
                  |L31.34|
;;;376        default:
;;;377          break;
000022  bf00              NOP      
                  |L31.36|
000024  bf00              NOP                            ;371
;;;378      }
;;;379    }
000026  4770              BX       lr
;;;380    
                          ENDP

                  |L31.40|
                          DCD      0x40023870

                          AREA ||i.RCC_LSICmd||, CODE, READONLY, ALIGN=2

                  RCC_LSICmd PROC
;;;392      */
;;;393    void RCC_LSICmd(FunctionalState NewState)
000000  4901              LDR      r1,|L32.8|
;;;394    {
;;;395      /* Check the parameters */
;;;396      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;397    
;;;398      *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;399    }
000004  4770              BX       lr
;;;400    
                          ENDP

000006  0000              DCW      0x0000
                  |L32.8|
                          DCD      0x42470e80

                          AREA ||i.RCC_MCO1Config||, CODE, READONLY, ALIGN=2

                  RCC_MCO1Config PROC
;;;542      */
;;;543    void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
000000  4602              MOV      r2,r0
;;;544    {
;;;545      uint32_t tmpreg = 0;
000002  2000              MOVS     r0,#0
;;;546      
;;;547      /* Check the parameters */
;;;548      assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
;;;549      assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));  
;;;550    
;;;551      tmpreg = RCC->CFGR;
000004  4b04              LDR      r3,|L33.24|
000006  6818              LDR      r0,[r3,#0]
;;;552    
;;;553      /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
;;;554      tmpreg &= CFGR_MCO1_RESET_MASK;
000008  f02060ec          BIC      r0,r0,#0x7600000
;;;555    
;;;556      /* Select MCO1 clock source and prescaler */
;;;557      tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
00000c  ea420301          ORR      r3,r2,r1
000010  4318              ORRS     r0,r0,r3
;;;558    
;;;559      /* Store the new value */
;;;560      RCC->CFGR = tmpreg;  
000012  4b01              LDR      r3,|L33.24|
000014  6018              STR      r0,[r3,#0]
;;;561    }
000016  4770              BX       lr
;;;562    
                          ENDP

                  |L33.24|
                          DCD      0x40023808

                          AREA ||i.RCC_MCO2Config||, CODE, READONLY, ALIGN=2

                  RCC_MCO2Config PROC
;;;580      */
;;;581    void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
000000  4602              MOV      r2,r0
;;;582    {
;;;583      uint32_t tmpreg = 0;
000002  2000              MOVS     r0,#0
;;;584      
;;;585      /* Check the parameters */
;;;586      assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
;;;587      assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
;;;588      
;;;589      tmpreg = RCC->CFGR;
000004  4b04              LDR      r3,|L34.24|
000006  6818              LDR      r0,[r3,#0]
;;;590      
;;;591      /* Clear MCO2 and MCO2PRE[2:0] bits */
;;;592      tmpreg &= CFGR_MCO2_RESET_MASK;
000008  f0204078          BIC      r0,r0,#0xf8000000
;;;593    
;;;594      /* Select MCO2 clock source and prescaler */
;;;595      tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
00000c  ea420301          ORR      r3,r2,r1
000010  4318              ORRS     r0,r0,r3
;;;596    
;;;597      /* Store the new value */
;;;598      RCC->CFGR = tmpreg;  
000012  4b01              LDR      r3,|L34.24|
000014  6018              STR      r0,[r3,#0]
;;;599    }
000016  4770              BX       lr
;;;600    
                          ENDP

                  |L34.24|
                          DCD      0x40023808

                          AREA ||i.RCC_PCLK1Config||, CODE, READONLY, ALIGN=2

                  RCC_PCLK1Config PROC
;;;771      */
;;;772    void RCC_PCLK1Config(uint32_t RCC_HCLK)
000000  4601              MOV      r1,r0
;;;773    {
;;;774      uint32_t tmpreg = 0;
000002  2000              MOVS     r0,#0
;;;775    
;;;776      /* Check the parameters */
;;;777      assert_param(IS_RCC_PCLK(RCC_HCLK));
;;;778    
;;;779      tmpreg = RCC->CFGR;
000004  4a03              LDR      r2,|L35.20|
000006  6810              LDR      r0,[r2,#0]
;;;780    
;;;781      /* Clear PPRE1[2:0] bits */
;;;782      tmpreg &= ~RCC_CFGR_PPRE1;
000008  f42050e0          BIC      r0,r0,#0x1c00
;;;783    
;;;784      /* Set PPRE1[2:0] bits according to RCC_HCLK value */
;;;785      tmpreg |= RCC_HCLK;
00000c  4308              ORRS     r0,r0,r1
;;;786    
;;;787      /* Store the new value */
;;;788      RCC->CFGR = tmpreg;
00000e  6010              STR      r0,[r2,#0]
;;;789    }
000010  4770              BX       lr
;;;790    
                          ENDP

000012  0000              DCW      0x0000
                  |L35.20|
                          DCD      0x40023808

                          AREA ||i.RCC_PCLK2Config||, CODE, READONLY, ALIGN=2

                  RCC_PCLK2Config PROC
;;;802      */
;;;803    void RCC_PCLK2Config(uint32_t RCC_HCLK)
000000  4601              MOV      r1,r0
;;;804    {
;;;805      uint32_t tmpreg = 0;
000002  2000              MOVS     r0,#0
;;;806    
;;;807      /* Check the parameters */
;;;808      assert_param(IS_RCC_PCLK(RCC_HCLK));
;;;809    
;;;810      tmpreg = RCC->CFGR;
000004  4a03              LDR      r2,|L36.20|
000006  6810              LDR      r0,[r2,#0]
;;;811    
;;;812      /* Clear PPRE2[2:0] bits */
;;;813      tmpreg &= ~RCC_CFGR_PPRE2;
000008  f4204060          BIC      r0,r0,#0xe000
;;;814    
;;;815      /* Set PPRE2[2:0] bits according to RCC_HCLK value */
;;;816      tmpreg |= RCC_HCLK << 3;
00000c  ea4000c1          ORR      r0,r0,r1,LSL #3
;;;817    
;;;818      /* Store the new value */
;;;819      RCC->CFGR = tmpreg;
000010  6010              STR      r0,[r2,#0]
;;;820    }
000012  4770              BX       lr
;;;821    
                          ENDP

                  |L36.20|
                          DCD      0x40023808

                          AREA ||i.RCC_PLLCmd||, CODE, READONLY, ALIGN=2

                  RCC_PLLCmd PROC
;;;458      */
;;;459    void RCC_PLLCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L37.8|
;;;460    {
;;;461      /* Check the parameters */
;;;462      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;463      *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
000002  6608              STR      r0,[r1,#0x60]
;;;464    }
000004  4770              BX       lr
;;;465    
                          ENDP

000006  0000              DCW      0x0000
                  |L37.8|
                          DCD      0x42470000

                          AREA ||i.RCC_PLLConfig||, CODE, READONLY, ALIGN=2

                  RCC_PLLConfig PROC
;;;435      */
;;;436    void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
000000  b530              PUSH     {r4,r5,lr}
;;;437    {
000002  f8ddc00c          LDR      r12,[sp,#0xc]
;;;438      /* Check the parameters */
;;;439      assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
;;;440      assert_param(IS_RCC_PLLM_VALUE(PLLM));
;;;441      assert_param(IS_RCC_PLLN_VALUE(PLLN));
;;;442      assert_param(IS_RCC_PLLP_VALUE(PLLP));
;;;443      assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
;;;444    
;;;445      RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
000006  ea411482          ORR      r4,r1,r2,LSL #6
00000a  2501              MOVS     r5,#1
00000c  ebc50553          RSB      r5,r5,r3,LSR #1
000010  ea444405          ORR      r4,r4,r5,LSL #16
000014  4304              ORRS     r4,r4,r0
000016  ea44640c          ORR      r4,r4,r12,LSL #24
00001a  4d01              LDR      r5,|L38.32|
00001c  602c              STR      r4,[r5,#0]
;;;446                     (PLLQ << 24);
;;;447    }
00001e  bd30              POP      {r4,r5,pc}
;;;448    
                          ENDP

                  |L38.32|
                          DCD      0x40023804

                          AREA ||i.RCC_PLLI2SCmd||, CODE, READONLY, ALIGN=2

                  RCC_PLLI2SCmd PROC
;;;499      */
;;;500    void RCC_PLLI2SCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L39.8|
;;;501    {
;;;502      /* Check the parameters */
;;;503      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;504      *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
000002  6688              STR      r0,[r1,#0x68]
;;;505    }
000004  4770              BX       lr
;;;506    
                          ENDP

000006  0000              DCW      0x0000
                  |L39.8|
                          DCD      0x42470000

                          AREA ||i.RCC_PLLI2SConfig||, CODE, READONLY, ALIGN=2

                  RCC_PLLI2SConfig PROC
;;;484      */
;;;485    void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
000000  0182              LSLS     r2,r0,#6
;;;486    {
;;;487      /* Check the parameters */
;;;488      assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
;;;489      assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
;;;490    
;;;491      RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
000002  ea427201          ORR      r2,r2,r1,LSL #28
000006  4b01              LDR      r3,|L40.12|
000008  601a              STR      r2,[r3,#0]
;;;492    }
00000a  4770              BX       lr
;;;493    
                          ENDP

                  |L40.12|
                          DCD      0x40023884

                          AREA ||i.RCC_RTCCLKCmd||, CODE, READONLY, ALIGN=2

                  RCC_RTCCLKCmd PROC
;;;1011     */
;;;1012   void RCC_RTCCLKCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L41.8|
;;;1013   {
;;;1014     /* Check the parameters */
;;;1015     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1016   
;;;1017     *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;1018   }
000004  4770              BX       lr
;;;1019   
                          ENDP

000006  0000              DCW      0x0000
                  |L41.8|
                          DCD      0x42470e3c

                          AREA ||i.RCC_RTCCLKConfig||, CODE, READONLY, ALIGN=2

                  RCC_RTCCLKConfig PROC
;;;979      */
;;;980    void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
000000  2100              MOVS     r1,#0
;;;981    {
;;;982      uint32_t tmpreg = 0;
;;;983    
;;;984      /* Check the parameters */
;;;985      assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
;;;986    
;;;987      if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
000002  f4007240          AND      r2,r0,#0x300
000006  f5b27f40          CMP      r2,#0x300
00000a  d108              BNE      |L42.30|
;;;988      { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
;;;989        tmpreg = RCC->CFGR;
00000c  4a09              LDR      r2,|L42.52|
00000e  6811              LDR      r1,[r2,#0]
;;;990    
;;;991        /* Clear RTCPRE[4:0] bits */
;;;992        tmpreg &= ~RCC_CFGR_RTCPRE;
000010  f42111f8          BIC      r1,r1,#0x1f0000
;;;993    
;;;994        /* Configure HSE division factor for RTC clock */
;;;995        tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
000014  4a08              LDR      r2,|L42.56|
000016  4002              ANDS     r2,r2,r0
000018  4311              ORRS     r1,r1,r2
;;;996    
;;;997        /* Store the new value */
;;;998        RCC->CFGR = tmpreg;
00001a  4a06              LDR      r2,|L42.52|
00001c  6011              STR      r1,[r2,#0]
                  |L42.30|
;;;999      }
;;;1000       
;;;1001     /* Select the RTC clock source */
;;;1002     RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
00001e  4a05              LDR      r2,|L42.52|
000020  3268              ADDS     r2,r2,#0x68
000022  6812              LDR      r2,[r2,#0]
000024  f3c0030b          UBFX     r3,r0,#0,#12
000028  431a              ORRS     r2,r2,r3
00002a  4b02              LDR      r3,|L42.52|
00002c  3368              ADDS     r3,r3,#0x68
00002e  601a              STR      r2,[r3,#0]
;;;1003   }
000030  4770              BX       lr
;;;1004   
                          ENDP

000032  0000              DCW      0x0000
                  |L42.52|
                          DCD      0x40023808
                  |L42.56|
                          DCD      0x0ffffcff

                          AREA ||i.RCC_SYSCLKConfig||, CODE, READONLY, ALIGN=2

                  RCC_SYSCLKConfig PROC
;;;686      */
;;;687    void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
000000  4601              MOV      r1,r0
;;;688    {
;;;689      uint32_t tmpreg = 0;
000002  2000              MOVS     r0,#0
;;;690    
;;;691      /* Check the parameters */
;;;692      assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
;;;693    
;;;694      tmpreg = RCC->CFGR;
000004  4a03              LDR      r2,|L43.20|
000006  6810              LDR      r0,[r2,#0]
;;;695    
;;;696      /* Clear SW[1:0] bits */
;;;697      tmpreg &= ~RCC_CFGR_SW;
000008  f0200003          BIC      r0,r0,#3
;;;698    
;;;699      /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
;;;700      tmpreg |= RCC_SYSCLKSource;
00000c  4308              ORRS     r0,r0,r1
;;;701    
;;;702      /* Store the new value */
;;;703      RCC->CFGR = tmpreg;
00000e  6010              STR      r0,[r2,#0]
;;;704    }
000010  4770              BX       lr
;;;705    
                          ENDP

000012  0000              DCW      0x0000
                  |L43.20|
                          DCD      0x40023808

                          AREA ||i.RCC_WaitForHSEStartUp||, CODE, READONLY, ALIGN=1

                  RCC_WaitForHSEStartUp PROC
;;;260      */
;;;261    ErrorStatus RCC_WaitForHSEStartUp(void)
000000  b570              PUSH     {r4-r6,lr}
;;;262    {
;;;263      __IO uint32_t startupcounter = 0;
000002  2400              MOVS     r4,#0
;;;264      ErrorStatus status = ERROR;
000004  2500              MOVS     r5,#0
;;;265      FlagStatus hsestatus = RESET;
000006  2600              MOVS     r6,#0
;;;266      /* Wait till HSE is ready and if Time out is reached exit */
;;;267      do
000008  bf00              NOP      
                  |L44.10|
;;;268      {
;;;269        hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
00000a  2031              MOVS     r0,#0x31
00000c  f7fffffe          BL       RCC_GetFlagStatus
000010  4606              MOV      r6,r0
;;;270        startupcounter++;
000012  1c64              ADDS     r4,r4,#1
;;;271      } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
000014  f5b46fa0          CMP      r4,#0x500
000018  d001              BEQ      |L44.30|
00001a  2e00              CMP      r6,#0
00001c  d0f5              BEQ      |L44.10|
                  |L44.30|
;;;272    
;;;273      if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
00001e  2031              MOVS     r0,#0x31
000020  f7fffffe          BL       RCC_GetFlagStatus
000024  b108              CBZ      r0,|L44.42|
;;;274      {
;;;275        status = SUCCESS;
000026  2501              MOVS     r5,#1
000028  e000              B        |L44.44|
                  |L44.42|
;;;276      }
;;;277      else
;;;278      {
;;;279        status = ERROR;
00002a  2500              MOVS     r5,#0
                  |L44.44|
;;;280      }
;;;281      return (status);
00002c  4628              MOV      r0,r5
;;;282    }
00002e  bd70              POP      {r4-r6,pc}
;;;283    
                          ENDP


                          AREA ||.data||, DATA, ALIGN=0

                  APBAHBPrescTable
000000  00000000          DCB      0x00,0x00,0x00,0x00
000004  01020304          DCB      0x01,0x02,0x03,0x04
000008  01020304          DCB      0x01,0x02,0x03,0x04
00000c  06070809          DCB      0x06,0x07,0x08,0x09

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_rcc.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_stm32f4xx_rcc_c_49e27980____REV16|
#line 114 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f4xx_rcc_c_49e27980____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_stm32f4xx_rcc_c_49e27980____REVSH|
#line 128
|__asm___15_stm32f4xx_rcc_c_49e27980____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
