; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\STM324xG_EVAL\stm32f4xx_pwr.o --asm_dir=.\STM324xG_EVAL\ --list_dir=.\STM324xG_EVAL\ --depend=.\STM324xG_EVAL\stm32f4xx_pwr.d --cpu=Cortex-M4.fp --apcs=interwork -O0 -Otime -I..\ -I..\..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\..\Utilities\STM32_EVAL\Common -I..\..\..\Utilities\STM32_EVAL\STM3240_41_G_EVAL -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F4xx -D__MICROLIB -DUSE_STM324xG_EVAL -DSTM32F4XX -DUSE_STDPERIPH_DRIVER --omf_browse=.\STM324xG_EVAL\stm32f4xx_pwr.crf ..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_pwr.c]
                          THUMB

                          AREA ||i.PWR_BackupAccessCmd||, CODE, READONLY, ALIGN=2

                  PWR_BackupAccessCmd PROC
;;;134      */
;;;135    void PWR_BackupAccessCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L1.8|
;;;136    {
;;;137      /* Check the parameters */
;;;138      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;139      
;;;140      *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
000002  6208              STR      r0,[r1,#0x20]
;;;141    }
000004  4770              BX       lr
;;;142    
                          ENDP

000006  0000              DCW      0x0000
                  |L1.8|
                          DCD      0x420e0000

                          AREA ||i.PWR_BackupRegulatorCmd||, CODE, READONLY, ALIGN=2

                  PWR_BackupRegulatorCmd PROC
;;;297      */
;;;298    void PWR_BackupRegulatorCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L2.8|
;;;299    {
;;;300      /* Check the parameters */
;;;301      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;302    
;;;303      *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;304    }
000004  4770              BX       lr
;;;305    
                          ENDP

000006  0000              DCW      0x0000
                  |L2.8|
                          DCD      0x420e00a4

                          AREA ||i.PWR_ClearFlag||, CODE, READONLY, ALIGN=2

                  PWR_ClearFlag PROC
;;;631      */
;;;632    void PWR_ClearFlag(uint32_t PWR_FLAG)
000000  4903              LDR      r1,|L3.16|
;;;633    {
;;;634      /* Check the parameters */
;;;635      assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
;;;636             
;;;637      PWR->CR |=  PWR_FLAG << 2;
000002  6809              LDR      r1,[r1,#0]
000004  ea410180          ORR      r1,r1,r0,LSL #2
000008  4a01              LDR      r2,|L3.16|
00000a  6011              STR      r1,[r2,#0]
;;;638    }
00000c  4770              BX       lr
;;;639    
                          ENDP

00000e  0000              DCW      0x0000
                  |L3.16|
                          DCD      0x40007000

                          AREA ||i.PWR_DeInit||, CODE, READONLY, ALIGN=1

                  PWR_DeInit PROC
;;;119      */
;;;120    void PWR_DeInit(void)
000000  b510              PUSH     {r4,lr}
;;;121    {
;;;122      RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
000002  2101              MOVS     r1,#1
000004  0708              LSLS     r0,r1,#28
000006  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;123      RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
00000a  2100              MOVS     r1,#0
00000c  f04f5080          MOV      r0,#0x10000000
000010  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;124    }
000014  bd10              POP      {r4,pc}
;;;125    
                          ENDP


                          AREA ||i.PWR_EnterSTANDBYMode||, CODE, READONLY, ALIGN=2

                  PWR_EnterSTANDBYMode PROC
;;;547      */
;;;548    void PWR_EnterSTANDBYMode(void)
000000  480a              LDR      r0,|L5.44|
;;;549    {
;;;550      /* Clear Wakeup flag */
;;;551      PWR->CR |= PWR_CR_CWUF;
000002  6800              LDR      r0,[r0,#0]
000004  f0400004          ORR      r0,r0,#4
000008  4908              LDR      r1,|L5.44|
00000a  6008              STR      r0,[r1,#0]
;;;552      
;;;553      /* Select STANDBY mode */
;;;554      PWR->CR |= PWR_CR_PDDS;
00000c  4608              MOV      r0,r1
00000e  6800              LDR      r0,[r0,#0]
000010  f0400002          ORR      r0,r0,#2
000014  6008              STR      r0,[r1,#0]
;;;555      
;;;556      /* Set SLEEPDEEP bit of Cortex System Control Register */
;;;557      SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
000016  4806              LDR      r0,|L5.48|
000018  6800              LDR      r0,[r0,#0]
00001a  f0400004          ORR      r0,r0,#4
00001e  4904              LDR      r1,|L5.48|
000020  6008              STR      r0,[r1,#0]
;;;558      
;;;559    /* This option is used to ensure that store operations are completed */
;;;560    #if defined ( __CC_ARM   )
;;;561      __force_stores();
000022  bf00              NOP      
000024  bf00              NOP      
;;;562    #endif
;;;563      /* Request Wait For Interrupt */
;;;564      __WFI();
000026  bf30              WFI      
;;;565    }
000028  4770              BX       lr
;;;566    
                          ENDP

00002a  0000              DCW      0x0000
                  |L5.44|
                          DCD      0x40007000
                  |L5.48|
                          DCD      0xe000ed10

                          AREA ||i.PWR_EnterSTOPMode||, CODE, READONLY, ALIGN=2

                  PWR_EnterSTOPMode PROC
;;;499      */
;;;500    void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
000000  b510              PUSH     {r4,lr}
;;;501    {
000002  4602              MOV      r2,r0
;;;502      uint32_t tmpreg = 0;
000004  2000              MOVS     r0,#0
;;;503      
;;;504      /* Check the parameters */
;;;505      assert_param(IS_PWR_REGULATOR(PWR_Regulator));
;;;506      assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
;;;507      
;;;508      /* Select the regulator state in STOP mode ---------------------------------*/
;;;509      tmpreg = PWR->CR;
000006  4b0c              LDR      r3,|L6.56|
000008  6818              LDR      r0,[r3,#0]
;;;510      /* Clear PDDS and LPDSR bits */
;;;511      tmpreg &= CR_DS_MASK;
00000a  f0200003          BIC      r0,r0,#3
;;;512      
;;;513      /* Set LPDSR bit according to PWR_Regulator value */
;;;514      tmpreg |= PWR_Regulator;
00000e  4310              ORRS     r0,r0,r2
;;;515      
;;;516      /* Store the new value */
;;;517      PWR->CR = tmpreg;
000010  6018              STR      r0,[r3,#0]
;;;518      
;;;519      /* Set SLEEPDEEP bit of Cortex System Control Register */
;;;520      SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
000012  4b0a              LDR      r3,|L6.60|
000014  681b              LDR      r3,[r3,#0]
000016  f0430304          ORR      r3,r3,#4
00001a  4c08              LDR      r4,|L6.60|
00001c  6023              STR      r3,[r4,#0]
;;;521      
;;;522      /* Select STOP mode entry --------------------------------------------------*/
;;;523      if(PWR_STOPEntry == PWR_STOPEntry_WFI)
00001e  2901              CMP      r1,#1
000020  d101              BNE      |L6.38|
;;;524      {   
;;;525        /* Request Wait For Interrupt */
;;;526        __WFI();
000022  bf30              WFI      
000024  e000              B        |L6.40|
                  |L6.38|
;;;527      }
;;;528      else
;;;529      {
;;;530        /* Request Wait For Event */
;;;531        __WFE();
000026  bf20              WFE      
                  |L6.40|
;;;532      }
;;;533      /* Reset SLEEPDEEP bit of Cortex System Control Register */
;;;534      SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
000028  4b04              LDR      r3,|L6.60|
00002a  681b              LDR      r3,[r3,#0]
00002c  f0230304          BIC      r3,r3,#4
000030  4c02              LDR      r4,|L6.60|
000032  6023              STR      r3,[r4,#0]
;;;535    }
000034  bd10              POP      {r4,pc}
;;;536    
                          ENDP

000036  0000              DCW      0x0000
                  |L6.56|
                          DCD      0x40007000
                  |L6.60|
                          DCD      0xe000ed10

                          AREA ||i.PWR_FlashPowerDownCmd||, CODE, READONLY, ALIGN=2

                  PWR_FlashPowerDownCmd PROC
;;;359      */
;;;360    void PWR_FlashPowerDownCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L7.8|
;;;361    {
;;;362      /* Check the parameters */
;;;363      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;364    
;;;365      *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
000002  6248              STR      r0,[r1,#0x24]
;;;366    }
000004  4770              BX       lr
;;;367    
                          ENDP

000006  0000              DCW      0x0000
                  |L7.8|
                          DCD      0x420e0000

                          AREA ||i.PWR_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  PWR_GetFlagStatus PROC
;;;604      */
;;;605    FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
000000  4601              MOV      r1,r0
;;;606    {
;;;607      FlagStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;608      
;;;609      /* Check the parameters */
;;;610      assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
;;;611      
;;;612      if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
000004  4a03              LDR      r2,|L8.20|
000006  6852              LDR      r2,[r2,#4]
000008  420a              TST      r2,r1
00000a  d001              BEQ      |L8.16|
;;;613      {
;;;614        bitstatus = SET;
00000c  2001              MOVS     r0,#1
00000e  e000              B        |L8.18|
                  |L8.16|
;;;615      }
;;;616      else
;;;617      {
;;;618        bitstatus = RESET;
000010  2000              MOVS     r0,#0
                  |L8.18|
;;;619      }
;;;620      /* Return the flag status */
;;;621      return bitstatus;
;;;622    }
000012  4770              BX       lr
;;;623    
                          ENDP

                  |L8.20|
                          DCD      0x40007000

                          AREA ||i.PWR_MainRegulatorModeConfig||, CODE, READONLY, ALIGN=2

                  PWR_MainRegulatorModeConfig PROC
;;;317      */
;;;318    void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
000000  b930              CBNZ     r0,|L9.16|
;;;319    {
;;;320      /* Check the parameters */
;;;321      assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
;;;322    
;;;323      if (PWR_Regulator_Voltage == PWR_Regulator_Voltage_Scale2)
;;;324      {
;;;325        PWR->CR &= ~PWR_Regulator_Voltage_Scale1;
000002  4907              LDR      r1,|L9.32|
000004  6809              LDR      r1,[r1,#0]
000006  f4214180          BIC      r1,r1,#0x4000
00000a  4a05              LDR      r2,|L9.32|
00000c  6011              STR      r1,[r2,#0]
00000e  e005              B        |L9.28|
                  |L9.16|
;;;326      }
;;;327      else
;;;328      {    
;;;329        PWR->CR |= PWR_Regulator_Voltage_Scale1;
000010  4903              LDR      r1,|L9.32|
000012  6809              LDR      r1,[r1,#0]
000014  f4414180          ORR      r1,r1,#0x4000
000018  4a01              LDR      r2,|L9.32|
00001a  6011              STR      r1,[r2,#0]
                  |L9.28|
;;;330      }
;;;331    }
00001c  4770              BX       lr
;;;332    
                          ENDP

00001e  0000              DCW      0x0000
                  |L9.32|
                          DCD      0x40007000

                          AREA ||i.PWR_PVDCmd||, CODE, READONLY, ALIGN=2

                  PWR_PVDCmd PROC
;;;205      */
;;;206    void PWR_PVDCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L10.8|
;;;207    {
;;;208      /* Check the parameters */
;;;209      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;210      
;;;211      *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
000002  6108              STR      r0,[r1,#0x10]
;;;212    }
000004  4770              BX       lr
;;;213    
                          ENDP

000006  0000              DCW      0x0000
                  |L10.8|
                          DCD      0x420e0000

                          AREA ||i.PWR_PVDLevelConfig||, CODE, READONLY, ALIGN=2

                  PWR_PVDLevelConfig PROC
;;;180      */
;;;181    void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
000000  4601              MOV      r1,r0
;;;182    {
;;;183      uint32_t tmpreg = 0;
000002  2000              MOVS     r0,#0
;;;184      
;;;185      /* Check the parameters */
;;;186      assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
;;;187      
;;;188      tmpreg = PWR->CR;
000004  4a03              LDR      r2,|L11.20|
000006  6810              LDR      r0,[r2,#0]
;;;189      
;;;190      /* Clear PLS[7:5] bits */
;;;191      tmpreg &= CR_PLS_MASK;
000008  f02000e0          BIC      r0,r0,#0xe0
;;;192      
;;;193      /* Set PLS[7:5] bits according to PWR_PVDLevel value */
;;;194      tmpreg |= PWR_PVDLevel;
00000c  4308              ORRS     r0,r0,r1
;;;195      
;;;196      /* Store the new value */
;;;197      PWR->CR = tmpreg;
00000e  6010              STR      r0,[r2,#0]
;;;198    }
000010  4770              BX       lr
;;;199    
                          ENDP

000012  0000              DCW      0x0000
                  |L11.20|
                          DCD      0x40007000

                          AREA ||i.PWR_WakeUpPinCmd||, CODE, READONLY, ALIGN=2

                  PWR_WakeUpPinCmd PROC
;;;239      */
;;;240    void PWR_WakeUpPinCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L12.8|
;;;241    {
;;;242      /* Check the parameters */  
;;;243      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;244    
;;;245      *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;246    }
000004  4770              BX       lr
;;;247    
                          ENDP

000006  0000              DCW      0x0000
                  |L12.8|
                          DCD      0x420e00a0

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_pwr.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_stm32f4xx_pwr_c_0c2a8b75____REV16|
#line 114 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f4xx_pwr_c_0c2a8b75____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_stm32f4xx_pwr_c_0c2a8b75____REVSH|
#line 128
|__asm___15_stm32f4xx_pwr_c_0c2a8b75____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
