; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\STM324xG_EVAL\stm32f4xx_fsmc.o --asm_dir=.\STM324xG_EVAL\ --list_dir=.\STM324xG_EVAL\ --depend=.\STM324xG_EVAL\stm32f4xx_fsmc.d --cpu=Cortex-M4.fp --apcs=interwork -O0 -Otime -I..\ -I..\..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\..\Utilities\STM32_EVAL\Common -I..\..\..\Utilities\STM32_EVAL\STM3240_41_G_EVAL -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F4xx -D__MICROLIB -DUSE_STM324xG_EVAL -DSTM32F4XX -DUSE_STDPERIPH_DRIVER --omf_browse=.\STM324xG_EVAL\stm32f4xx_fsmc.crf ..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_fsmc.c]
                          THUMB

                          AREA ||i.FSMC_ClearFlag||, CODE, READONLY, ALIGN=2

                  FSMC_ClearFlag PROC
;;;858      */
;;;859    void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
000000  2810              CMP      r0,#0x10
;;;860    {
;;;861     /* Check the parameters */
;;;862      assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
;;;863      assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
;;;864        
;;;865      if(FSMC_Bank == FSMC_Bank2_NAND)
000002  d107              BNE      |L1.20|
;;;866      {
;;;867        FSMC_Bank2->SR2 &= ~FSMC_FLAG; 
000004  f04f4220          MOV      r2,#0xa0000000
000008  6e52              LDR      r2,[r2,#0x64]
00000a  438a              BICS     r2,r2,r1
00000c  f04f4320          MOV      r3,#0xa0000000
000010  665a              STR      r2,[r3,#0x64]
000012  e013              B        |L1.60|
                  |L1.20|
;;;868      }  
;;;869      else if(FSMC_Bank == FSMC_Bank3_NAND)
000014  f5b07f80          CMP      r0,#0x100
000018  d108              BNE      |L1.44|
;;;870      {
;;;871        FSMC_Bank3->SR3 &= ~FSMC_FLAG;
00001a  4a09              LDR      r2,|L1.64|
00001c  6812              LDR      r2,[r2,#0]
00001e  ea220201          BIC      r2,r2,r1
000022  f04f4320          MOV      r3,#0xa0000000
000026  f8c32084          STR      r2,[r3,#0x84]
00002a  e007              B        |L1.60|
                  |L1.44|
;;;872      }
;;;873      /* FSMC_Bank4_PCCARD*/
;;;874      else
;;;875      {
;;;876        FSMC_Bank4->SR4 &= ~FSMC_FLAG;
00002c  4a05              LDR      r2,|L1.68|
00002e  6812              LDR      r2,[r2,#0]
000030  ea220201          BIC      r2,r2,r1
000034  f04f4320          MOV      r3,#0xa0000000
000038  f8c320a4          STR      r2,[r3,#0xa4]
                  |L1.60|
;;;877      }
;;;878    }
00003c  4770              BX       lr
;;;879    
                          ENDP

00003e  0000              DCW      0x0000
                  |L1.64|
                          DCD      0xa0000084
                  |L1.68|
                          DCD      0xa00000a4

                          AREA ||i.FSMC_ClearITPendingBit||, CODE, READONLY, ALIGN=2

                  FSMC_ClearITPendingBit PROC
;;;944      */
;;;945    void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
000000  2810              CMP      r0,#0x10
;;;946    {
;;;947      /* Check the parameters */
;;;948      assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
;;;949      assert_param(IS_FSMC_IT(FSMC_IT));
;;;950        
;;;951      if(FSMC_Bank == FSMC_Bank2_NAND)
000002  d108              BNE      |L2.22|
;;;952      {
;;;953        FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); 
000004  f04f4220          MOV      r2,#0xa0000000
000008  6e52              LDR      r2,[r2,#0x64]
00000a  ea2202d1          BIC      r2,r2,r1,LSR #3
00000e  f04f4320          MOV      r3,#0xa0000000
000012  665a              STR      r2,[r3,#0x64]
000014  e013              B        |L2.62|
                  |L2.22|
;;;954      }  
;;;955      else if(FSMC_Bank == FSMC_Bank3_NAND)
000016  f5b07f80          CMP      r0,#0x100
00001a  d108              BNE      |L2.46|
;;;956      {
;;;957        FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
00001c  4a08              LDR      r2,|L2.64|
00001e  6812              LDR      r2,[r2,#0]
000020  ea2202d1          BIC      r2,r2,r1,LSR #3
000024  f04f4320          MOV      r3,#0xa0000000
000028  f8c32084          STR      r2,[r3,#0x84]
00002c  e007              B        |L2.62|
                  |L2.46|
;;;958      }
;;;959      /* FSMC_Bank4_PCCARD*/
;;;960      else
;;;961      {
;;;962        FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
00002e  4a05              LDR      r2,|L2.68|
000030  6812              LDR      r2,[r2,#0]
000032  ea2202d1          BIC      r2,r2,r1,LSR #3
000036  f04f4320          MOV      r3,#0xa0000000
00003a  f8c320a4          STR      r2,[r3,#0xa4]
                  |L2.62|
;;;963      }
;;;964    }
00003e  4770              BX       lr
;;;965    
                          ENDP

                  |L2.64|
                          DCD      0xa0000084
                  |L2.68|
                          DCD      0xa00000a4

                          AREA ||i.FSMC_GetECC||, CODE, READONLY, ALIGN=2

                  FSMC_GetECC PROC
;;;542      */
;;;543    uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
000000  4601              MOV      r1,r0
;;;544    {
;;;545      uint32_t eccval = 0x00000000;
000002  2000              MOVS     r0,#0
;;;546      
;;;547      if(FSMC_Bank == FSMC_Bank2_NAND)
000004  2910              CMP      r1,#0x10
000006  d103              BNE      |L3.16|
;;;548      {
;;;549        /* Get the ECCR2 register value */
;;;550        eccval = FSMC_Bank2->ECCR2;
000008  f04f4220          MOV      r2,#0xa0000000
00000c  6f50              LDR      r0,[r2,#0x74]
00000e  e001              B        |L3.20|
                  |L3.16|
;;;551      }
;;;552      else
;;;553      {
;;;554        /* Get the ECCR3 register value */
;;;555        eccval = FSMC_Bank3->ECCR3;
000010  4a01              LDR      r2,|L3.24|
000012  6810              LDR      r0,[r2,#0]
                  |L3.20|
;;;556      }
;;;557      /* Return the error correction code value */
;;;558      return(eccval);
;;;559    }
000014  4770              BX       lr
;;;560    /**
                          ENDP

000016  0000              DCW      0x0000
                  |L3.24|
                          DCD      0xa0000094

                          AREA ||i.FSMC_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  FSMC_GetFlagStatus PROC
;;;808      */
;;;809    FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
000000  b510              PUSH     {r4,lr}
;;;810    {
000002  4602              MOV      r2,r0
;;;811      FlagStatus bitstatus = RESET;
000004  2000              MOVS     r0,#0
;;;812      uint32_t tmpsr = 0x00000000;
000006  2300              MOVS     r3,#0
;;;813      
;;;814      /* Check the parameters */
;;;815      assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
;;;816      assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
;;;817      
;;;818      if(FSMC_Bank == FSMC_Bank2_NAND)
000008  2a10              CMP      r2,#0x10
00000a  d103              BNE      |L4.20|
;;;819      {
;;;820        tmpsr = FSMC_Bank2->SR2;
00000c  f04f4420          MOV      r4,#0xa0000000
000010  6e63              LDR      r3,[r4,#0x64]
000012  e007              B        |L4.36|
                  |L4.20|
;;;821      }  
;;;822      else if(FSMC_Bank == FSMC_Bank3_NAND)
000014  f5b27f80          CMP      r2,#0x100
000018  d102              BNE      |L4.32|
;;;823      {
;;;824        tmpsr = FSMC_Bank3->SR3;
00001a  4c05              LDR      r4,|L4.48|
00001c  6823              LDR      r3,[r4,#0]
00001e  e001              B        |L4.36|
                  |L4.32|
;;;825      }
;;;826      /* FSMC_Bank4_PCCARD*/
;;;827      else
;;;828      {
;;;829        tmpsr = FSMC_Bank4->SR4;
000020  4c04              LDR      r4,|L4.52|
000022  6823              LDR      r3,[r4,#0]
                  |L4.36|
;;;830      } 
;;;831      
;;;832      /* Get the flag status */
;;;833      if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
000024  420b              TST      r3,r1
000026  d001              BEQ      |L4.44|
;;;834      {
;;;835        bitstatus = SET;
000028  2001              MOVS     r0,#1
00002a  e000              B        |L4.46|
                  |L4.44|
;;;836      }
;;;837      else
;;;838      {
;;;839        bitstatus = RESET;
00002c  2000              MOVS     r0,#0
                  |L4.46|
;;;840      }
;;;841      /* Return the flag status */
;;;842      return bitstatus;
;;;843    }
00002e  bd10              POP      {r4,pc}
;;;844    
                          ENDP

                  |L4.48|
                          DCD      0xa0000084
                  |L4.52|
                          DCD      0xa00000a4

                          AREA ||i.FSMC_GetITStatus||, CODE, READONLY, ALIGN=2

                  FSMC_GetITStatus PROC
;;;893      */
;;;894    ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
000000  b530              PUSH     {r4,r5,lr}
;;;895    {
000002  4602              MOV      r2,r0
;;;896      ITStatus bitstatus = RESET;
000004  2000              MOVS     r0,#0
;;;897      uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; 
000006  2300              MOVS     r3,#0
000008  2400              MOVS     r4,#0
00000a  4684              MOV      r12,r0
;;;898      
;;;899      /* Check the parameters */
;;;900      assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
;;;901      assert_param(IS_FSMC_GET_IT(FSMC_IT));
;;;902      
;;;903      if(FSMC_Bank == FSMC_Bank2_NAND)
00000c  2a10              CMP      r2,#0x10
00000e  d103              BNE      |L5.24|
;;;904      {
;;;905        tmpsr = FSMC_Bank2->SR2;
000010  f04f4520          MOV      r5,#0xa0000000
000014  6e6b              LDR      r3,[r5,#0x64]
000016  e007              B        |L5.40|
                  |L5.24|
;;;906      }  
;;;907      else if(FSMC_Bank == FSMC_Bank3_NAND)
000018  f5b27f80          CMP      r2,#0x100
00001c  d102              BNE      |L5.36|
;;;908      {
;;;909        tmpsr = FSMC_Bank3->SR3;
00001e  4d08              LDR      r5,|L5.64|
000020  682b              LDR      r3,[r5,#0]
000022  e001              B        |L5.40|
                  |L5.36|
;;;910      }
;;;911      /* FSMC_Bank4_PCCARD*/
;;;912      else
;;;913      {
;;;914        tmpsr = FSMC_Bank4->SR4;
000024  4d07              LDR      r5,|L5.68|
000026  682b              LDR      r3,[r5,#0]
                  |L5.40|
;;;915      } 
;;;916      
;;;917      itstatus = tmpsr & FSMC_IT;
000028  ea030401          AND      r4,r3,r1
;;;918      
;;;919      itenable = tmpsr & (FSMC_IT >> 3);
00002c  ea030cd1          AND      r12,r3,r1,LSR #3
;;;920      if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
000030  b124              CBZ      r4,|L5.60|
000032  f1bc0f00          CMP      r12,#0
000036  d001              BEQ      |L5.60|
;;;921      {
;;;922        bitstatus = SET;
000038  2001              MOVS     r0,#1
00003a  e000              B        |L5.62|
                  |L5.60|
;;;923      }
;;;924      else
;;;925      {
;;;926        bitstatus = RESET;
00003c  2000              MOVS     r0,#0
                  |L5.62|
;;;927      }
;;;928      return bitstatus; 
;;;929    }
00003e  bd30              POP      {r4,r5,pc}
;;;930    
                          ENDP

                  |L5.64|
                          DCD      0xa0000084
                  |L5.68|
                          DCD      0xa00000a4

                          AREA ||i.FSMC_ITConfig||, CODE, READONLY, ALIGN=2

                  FSMC_ITConfig PROC
;;;748      */
;;;749    void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
000000  b510              PUSH     {r4,lr}
;;;750    {
;;;751      assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
;;;752      assert_param(IS_FSMC_IT(FSMC_IT));	
;;;753      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;754      
;;;755      if (NewState != DISABLE)
000002  b1f2              CBZ      r2,|L6.66|
;;;756      {
;;;757        /* Enable the selected FSMC_Bank2 interrupts */
;;;758        if(FSMC_Bank == FSMC_Bank2_NAND)
000004  2810              CMP      r0,#0x10
000006  d107              BNE      |L6.24|
;;;759        {
;;;760          FSMC_Bank2->SR2 |= FSMC_IT;
000008  f04f4320          MOV      r3,#0xa0000000
00000c  6e5b              LDR      r3,[r3,#0x64]
00000e  430b              ORRS     r3,r3,r1
000010  f04f4420          MOV      r4,#0xa0000000
000014  6663              STR      r3,[r4,#0x64]
000016  e032              B        |L6.126|
                  |L6.24|
;;;761        }
;;;762        /* Enable the selected FSMC_Bank3 interrupts */
;;;763        else if (FSMC_Bank == FSMC_Bank3_NAND)
000018  f5b07f80          CMP      r0,#0x100
00001c  d108              BNE      |L6.48|
;;;764        {
;;;765          FSMC_Bank3->SR3 |= FSMC_IT;
00001e  4b18              LDR      r3,|L6.128|
000020  681b              LDR      r3,[r3,#0]
000022  ea430301          ORR      r3,r3,r1
000026  f04f4420          MOV      r4,#0xa0000000
00002a  f8c43084          STR      r3,[r4,#0x84]
00002e  e026              B        |L6.126|
                  |L6.48|
;;;766        }
;;;767        /* Enable the selected FSMC_Bank4 interrupts */
;;;768        else
;;;769        {
;;;770          FSMC_Bank4->SR4 |= FSMC_IT;    
000030  4b14              LDR      r3,|L6.132|
000032  681b              LDR      r3,[r3,#0]
000034  ea430301          ORR      r3,r3,r1
000038  f04f4420          MOV      r4,#0xa0000000
00003c  f8c430a4          STR      r3,[r4,#0xa4]
000040  e01d              B        |L6.126|
                  |L6.66|
;;;771        }
;;;772      }
;;;773      else
;;;774      {
;;;775        /* Disable the selected FSMC_Bank2 interrupts */
;;;776        if(FSMC_Bank == FSMC_Bank2_NAND)
000042  2810              CMP      r0,#0x10
000044  d107              BNE      |L6.86|
;;;777        {
;;;778          
;;;779          FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
000046  f04f4320          MOV      r3,#0xa0000000
00004a  6e5b              LDR      r3,[r3,#0x64]
00004c  438b              BICS     r3,r3,r1
00004e  f04f4420          MOV      r4,#0xa0000000
000052  6663              STR      r3,[r4,#0x64]
000054  e013              B        |L6.126|
                  |L6.86|
;;;780        }
;;;781        /* Disable the selected FSMC_Bank3 interrupts */
;;;782        else if (FSMC_Bank == FSMC_Bank3_NAND)
000056  f5b07f80          CMP      r0,#0x100
00005a  d108              BNE      |L6.110|
;;;783        {
;;;784          FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
00005c  4b08              LDR      r3,|L6.128|
00005e  681b              LDR      r3,[r3,#0]
000060  ea230301          BIC      r3,r3,r1
000064  f04f4420          MOV      r4,#0xa0000000
000068  f8c43084          STR      r3,[r4,#0x84]
00006c  e007              B        |L6.126|
                  |L6.110|
;;;785        }
;;;786        /* Disable the selected FSMC_Bank4 interrupts */
;;;787        else
;;;788        {
;;;789          FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    
00006e  4b05              LDR      r3,|L6.132|
000070  681b              LDR      r3,[r3,#0]
000072  ea230301          BIC      r3,r3,r1
000076  f04f4420          MOV      r4,#0xa0000000
00007a  f8c430a4          STR      r3,[r4,#0xa4]
                  |L6.126|
;;;790        }
;;;791      }
;;;792    }
00007e  bd10              POP      {r4,pc}
;;;793    
                          ENDP

                  |L6.128|
                          DCD      0xa0000084
                  |L6.132|
                          DCD      0xa00000a4

                          AREA ||i.FSMC_NANDCmd||, CODE, READONLY, ALIGN=2

                  FSMC_NANDCmd PROC
;;;463      */
;;;464    void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
000000  b199              CBZ      r1,|L7.42|
;;;465    {
;;;466      assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;467      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;468      
;;;469      if (NewState != DISABLE)
;;;470      {
;;;471        /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
;;;472        if(FSMC_Bank == FSMC_Bank2_NAND)
000002  2810              CMP      r0,#0x10
000004  d108              BNE      |L7.24|
;;;473        {
;;;474          FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
000006  f04f4220          MOV      r2,#0xa0000000
00000a  6e12              LDR      r2,[r2,#0x60]
00000c  f0420204          ORR      r2,r2,#4
000010  f04f4320          MOV      r3,#0xa0000000
000014  661a              STR      r2,[r3,#0x60]
000016  e01c              B        |L7.82|
                  |L7.24|
;;;475        }
;;;476        else
;;;477        {
;;;478          FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
000018  4a0e              LDR      r2,|L7.84|
00001a  6812              LDR      r2,[r2,#0]
00001c  f0420204          ORR      r2,r2,#4
000020  f04f4320          MOV      r3,#0xa0000000
000024  f8c32080          STR      r2,[r3,#0x80]
000028  e013              B        |L7.82|
                  |L7.42|
;;;479        }
;;;480      }
;;;481      else
;;;482      {
;;;483        /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
;;;484        if(FSMC_Bank == FSMC_Bank2_NAND)
00002a  2810              CMP      r0,#0x10
00002c  d108              BNE      |L7.64|
;;;485        {
;;;486          FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
00002e  f04f4220          MOV      r2,#0xa0000000
000032  6e12              LDR      r2,[r2,#0x60]
000034  4b08              LDR      r3,|L7.88|
000036  401a              ANDS     r2,r2,r3
000038  f04f4320          MOV      r3,#0xa0000000
00003c  661a              STR      r2,[r3,#0x60]
00003e  e008              B        |L7.82|
                  |L7.64|
;;;487        }
;;;488        else
;;;489        {
;;;490          FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
000040  4a04              LDR      r2,|L7.84|
000042  6812              LDR      r2,[r2,#0]
000044  4b04              LDR      r3,|L7.88|
000046  ea020203          AND      r2,r2,r3
00004a  f04f4320          MOV      r3,#0xa0000000
00004e  f8c32080          STR      r2,[r3,#0x80]
                  |L7.82|
;;;491        }
;;;492      }
;;;493    }
000052  4770              BX       lr
;;;494    /**
                          ENDP

                  |L7.84|
                          DCD      0xa0000080
                  |L7.88|
                          DCD      0x000ffffb

                          AREA ||i.FSMC_NANDDeInit||, CODE, READONLY, ALIGN=2

                  FSMC_NANDDeInit PROC
;;;338      */
;;;339    void FSMC_NANDDeInit(uint32_t FSMC_Bank)
000000  2810              CMP      r0,#0x10
;;;340    {
;;;341      /* Check the parameter */
;;;342      assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;343      
;;;344      if(FSMC_Bank == FSMC_Bank2_NAND)
000002  d10a              BNE      |L8.26|
;;;345      {
;;;346        /* Set the FSMC_Bank2 registers to their reset values */
;;;347        FSMC_Bank2->PCR2 = 0x00000018;
000004  2118              MOVS     r1,#0x18
000006  f04f4220          MOV      r2,#0xa0000000
00000a  6611              STR      r1,[r2,#0x60]
;;;348        FSMC_Bank2->SR2 = 0x00000040;
00000c  2140              MOVS     r1,#0x40
00000e  6651              STR      r1,[r2,#0x64]
;;;349        FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
000010  f04f31fc          MOV      r1,#0xfcfcfcfc
000014  6691              STR      r1,[r2,#0x68]
;;;350        FSMC_Bank2->PATT2 = 0xFCFCFCFC;  
000016  66d1              STR      r1,[r2,#0x6c]
000018  e010              B        |L8.60|
                  |L8.26|
;;;351      }
;;;352      /* FSMC_Bank3_NAND */  
;;;353      else
;;;354      {
;;;355        /* Set the FSMC_Bank3 registers to their reset values */
;;;356        FSMC_Bank3->PCR3 = 0x00000018;
00001a  2118              MOVS     r1,#0x18
00001c  4a08              LDR      r2,|L8.64|
00001e  6011              STR      r1,[r2,#0]
;;;357        FSMC_Bank3->SR3 = 0x00000040;
000020  f04f0140          MOV      r1,#0x40
000024  f04f4220          MOV      r2,#0xa0000000
000028  f8c21084          STR      r1,[r2,#0x84]
;;;358        FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
00002c  f04f31fc          MOV      r1,#0xfcfcfcfc
000030  4a04              LDR      r2,|L8.68|
000032  6011              STR      r1,[r2,#0]
;;;359        FSMC_Bank3->PATT3 = 0xFCFCFCFC; 
000034  f04f4220          MOV      r2,#0xa0000000
000038  f8c2108c          STR      r1,[r2,#0x8c]
                  |L8.60|
;;;360      }  
;;;361    }
00003c  4770              BX       lr
;;;362    
                          ENDP

00003e  0000              DCW      0x0000
                  |L8.64|
                          DCD      0xa0000080
                  |L8.68|
                          DCD      0xa0000088

                          AREA ||i.FSMC_NANDECCCmd||, CODE, READONLY, ALIGN=2

                  FSMC_NANDECCCmd PROC
;;;503      */
;;;504    void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
000000  b199              CBZ      r1,|L9.42|
;;;505    {
;;;506      assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;507      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;508      
;;;509      if (NewState != DISABLE)
;;;510      {
;;;511        /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
;;;512        if(FSMC_Bank == FSMC_Bank2_NAND)
000002  2810              CMP      r0,#0x10
000004  d108              BNE      |L9.24|
;;;513        {
;;;514          FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
000006  f04f4220          MOV      r2,#0xa0000000
00000a  6e12              LDR      r2,[r2,#0x60]
00000c  f0420240          ORR      r2,r2,#0x40
000010  f04f4320          MOV      r3,#0xa0000000
000014  661a              STR      r2,[r3,#0x60]
000016  e01c              B        |L9.82|
                  |L9.24|
;;;515        }
;;;516        else
;;;517        {
;;;518          FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
000018  4a0e              LDR      r2,|L9.84|
00001a  6812              LDR      r2,[r2,#0]
00001c  f0420240          ORR      r2,r2,#0x40
000020  f04f4320          MOV      r3,#0xa0000000
000024  f8c32080          STR      r2,[r3,#0x80]
000028  e013              B        |L9.82|
                  |L9.42|
;;;519        }
;;;520      }
;;;521      else
;;;522      {
;;;523        /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
;;;524        if(FSMC_Bank == FSMC_Bank2_NAND)
00002a  2810              CMP      r0,#0x10
00002c  d108              BNE      |L9.64|
;;;525        {
;;;526          FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
00002e  f04f4220          MOV      r2,#0xa0000000
000032  6e12              LDR      r2,[r2,#0x60]
000034  4b08              LDR      r3,|L9.88|
000036  401a              ANDS     r2,r2,r3
000038  f04f4320          MOV      r3,#0xa0000000
00003c  661a              STR      r2,[r3,#0x60]
00003e  e008              B        |L9.82|
                  |L9.64|
;;;527        }
;;;528        else
;;;529        {
;;;530          FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
000040  4a04              LDR      r2,|L9.84|
000042  6812              LDR      r2,[r2,#0]
000044  4b04              LDR      r3,|L9.88|
000046  ea020203          AND      r2,r2,r3
00004a  f04f4320          MOV      r3,#0xa0000000
00004e  f8c32080          STR      r2,[r3,#0x80]
                  |L9.82|
;;;531        }
;;;532      }
;;;533    }
000052  4770              BX       lr
;;;534    
                          ENDP

                  |L9.84|
                          DCD      0xa0000080
                  |L9.88|
                          DCD      0x000fffbf

                          AREA ||i.FSMC_NANDInit||, CODE, READONLY, ALIGN=2

                  FSMC_NANDInit PROC
;;;369      */
;;;370    void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;371    {
;;;372      uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 
000002  2100              MOVS     r1,#0
000004  2200              MOVS     r2,#0
000006  2300              MOVS     r3,#0
;;;373        
;;;374      /* Check the parameters */
;;;375      assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
;;;376      assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
;;;377      assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
;;;378      assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
;;;379      assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
;;;380      assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
;;;381      assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
;;;382      assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
;;;383      assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
;;;384      assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
;;;385      assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
;;;386      assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
;;;387      assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
;;;388      assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
;;;389      assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
;;;390      
;;;391      /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
;;;392      tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
000008  6844              LDR      r4,[r0,#4]
00000a  f0440408          ORR      r4,r4,#8
00000e  6885              LDR      r5,[r0,#8]
000010  432c              ORRS     r4,r4,r5
000012  68c5              LDR      r5,[r0,#0xc]
000014  432c              ORRS     r4,r4,r5
000016  6905              LDR      r5,[r0,#0x10]
000018  432c              ORRS     r4,r4,r5
00001a  6945              LDR      r5,[r0,#0x14]
00001c  ea442445          ORR      r4,r4,r5,LSL #9
000020  6985              LDR      r5,[r0,#0x18]
000022  ea443145          ORR      r1,r4,r5,LSL #13
;;;393                PCR_MEMORYTYPE_NAND |
;;;394                FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
;;;395                FSMC_NANDInitStruct->FSMC_ECC |
;;;396                FSMC_NANDInitStruct->FSMC_ECCPageSize |
;;;397                (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
;;;398                (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
;;;399                
;;;400      /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
;;;401      tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
000026  69c4              LDR      r4,[r0,#0x1c]
000028  6824              LDR      r4,[r4,#0]
00002a  69c5              LDR      r5,[r0,#0x1c]
00002c  686d              LDR      r5,[r5,#4]
00002e  ea442405          ORR      r4,r4,r5,LSL #8
000032  69c5              LDR      r5,[r0,#0x1c]
000034  68ad              LDR      r5,[r5,#8]
000036  ea444405          ORR      r4,r4,r5,LSL #16
00003a  69c5              LDR      r5,[r0,#0x1c]
00003c  68ed              LDR      r5,[r5,#0xc]
00003e  ea446205          ORR      r2,r4,r5,LSL #24
;;;402                (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;403                (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;404                (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
;;;405                
;;;406      /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
;;;407      tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
000042  6a04              LDR      r4,[r0,#0x20]
000044  6824              LDR      r4,[r4,#0]
000046  6a05              LDR      r5,[r0,#0x20]
000048  686d              LDR      r5,[r5,#4]
00004a  ea442405          ORR      r4,r4,r5,LSL #8
00004e  6a05              LDR      r5,[r0,#0x20]
000050  68ad              LDR      r5,[r5,#8]
000052  ea444405          ORR      r4,r4,r5,LSL #16
000056  6a05              LDR      r5,[r0,#0x20]
000058  68ed              LDR      r5,[r5,#0xc]
00005a  ea446305          ORR      r3,r4,r5,LSL #24
;;;408                (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;409                (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;410                (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;411      
;;;412      if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
00005e  6804              LDR      r4,[r0,#0]
000060  2c10              CMP      r4,#0x10
000062  d105              BNE      |L10.112|
;;;413      {
;;;414        /* FSMC_Bank2_NAND registers configuration */
;;;415        FSMC_Bank2->PCR2 = tmppcr;
000064  f04f4420          MOV      r4,#0xa0000000
000068  6621              STR      r1,[r4,#0x60]
;;;416        FSMC_Bank2->PMEM2 = tmppmem;
00006a  66a2              STR      r2,[r4,#0x68]
;;;417        FSMC_Bank2->PATT2 = tmppatt;
00006c  66e3              STR      r3,[r4,#0x6c]
00006e  e007              B        |L10.128|
                  |L10.112|
;;;418      }
;;;419      else
;;;420      {
;;;421        /* FSMC_Bank3_NAND registers configuration */
;;;422        FSMC_Bank3->PCR3 = tmppcr;
000070  4c04              LDR      r4,|L10.132|
000072  6021              STR      r1,[r4,#0]
;;;423        FSMC_Bank3->PMEM3 = tmppmem;
000074  f04f4420          MOV      r4,#0xa0000000
000078  f8c42088          STR      r2,[r4,#0x88]
;;;424        FSMC_Bank3->PATT3 = tmppatt;
00007c  4c02              LDR      r4,|L10.136|
00007e  6023              STR      r3,[r4,#0]
                  |L10.128|
;;;425      }
;;;426    }
000080  bd30              POP      {r4,r5,pc}
;;;427    
                          ENDP

000082  0000              DCW      0x0000
                  |L10.132|
                          DCD      0xa0000080
                  |L10.136|
                          DCD      0xa000008c

                          AREA ||i.FSMC_NANDStructInit||, CODE, READONLY, ALIGN=1

                  FSMC_NANDStructInit PROC
;;;434      */
;;;435    void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
000000  2110              MOVS     r1,#0x10
;;;436    { 
;;;437      /* Reset NAND Init structure parameters values */
;;;438      FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
000002  6001              STR      r1,[r0,#0]
;;;439      FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
000004  2100              MOVS     r1,#0
000006  6041              STR      r1,[r0,#4]
;;;440      FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
000008  6081              STR      r1,[r0,#8]
;;;441      FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
00000a  60c1              STR      r1,[r0,#0xc]
;;;442      FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
00000c  6101              STR      r1,[r0,#0x10]
;;;443      FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
00000e  6141              STR      r1,[r0,#0x14]
;;;444      FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
000010  6181              STR      r1,[r0,#0x18]
;;;445      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000012  21fc              MOVS     r1,#0xfc
000014  69c2              LDR      r2,[r0,#0x1c]
000016  6011              STR      r1,[r2,#0]
;;;446      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
000018  69c2              LDR      r2,[r0,#0x1c]
00001a  6051              STR      r1,[r2,#4]
;;;447      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00001c  69c2              LDR      r2,[r0,#0x1c]
00001e  6091              STR      r1,[r2,#8]
;;;448      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000020  69c2              LDR      r2,[r0,#0x1c]
000022  60d1              STR      r1,[r2,#0xc]
;;;449      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000024  6a02              LDR      r2,[r0,#0x20]
000026  6011              STR      r1,[r2,#0]
;;;450      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
000028  6a02              LDR      r2,[r0,#0x20]
00002a  6051              STR      r1,[r2,#4]
;;;451      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00002c  6a02              LDR      r2,[r0,#0x20]
00002e  6091              STR      r1,[r2,#8]
;;;452      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	  
000030  6a02              LDR      r2,[r0,#0x20]
000032  60d1              STR      r1,[r2,#0xc]
;;;453    }
000034  4770              BX       lr
;;;454    
                          ENDP


                          AREA ||i.FSMC_NORSRAMCmd||, CODE, READONLY, ALIGN=2

                  FSMC_NORSRAMCmd PROC
;;;267      */
;;;268    void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
000000  b151              CBZ      r1,|L12.24|
;;;269    {
;;;270      assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
;;;271      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;272      
;;;273      if (NewState != DISABLE)
;;;274      {
;;;275        /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
;;;276        FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
000002  f04f4220          MOV      r2,#0xa0000000
000006  f8522020          LDR      r2,[r2,r0,LSL #2]
00000a  f0420201          ORR      r2,r2,#1
00000e  f04f4320          MOV      r3,#0xa0000000
000012  f8432020          STR      r2,[r3,r0,LSL #2]
000016  e009              B        |L12.44|
                  |L12.24|
;;;277      }
;;;278      else
;;;279      {
;;;280        /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
;;;281        FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
000018  f04f4220          MOV      r2,#0xa0000000
00001c  f8522020          LDR      r2,[r2,r0,LSL #2]
000020  4b03              LDR      r3,|L12.48|
000022  401a              ANDS     r2,r2,r3
000024  f04f4320          MOV      r3,#0xa0000000
000028  f8432020          STR      r2,[r3,r0,LSL #2]
                  |L12.44|
;;;282      }
;;;283    }
00002c  4770              BX       lr
;;;284    /**
                          ENDP

00002e  0000              DCW      0x0000
                  |L12.48|
                          DCD      0x000ffffe

                          AREA ||i.FSMC_NORSRAMDeInit||, CODE, READONLY, ALIGN=1

                  FSMC_NORSRAMDeInit PROC
;;;115      */
;;;116    void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
000000  b930              CBNZ     r0,|L13.16|
;;;117    {
;;;118      /* Check the parameter */
;;;119      assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
;;;120      
;;;121      /* FSMC_Bank1_NORSRAM1 */
;;;122      if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
;;;123      {
;;;124        FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    
000002  f24301db          MOV      r1,#0x30db
000006  f04f4220          MOV      r2,#0xa0000000
00000a  f8421020          STR      r1,[r2,r0,LSL #2]
00000e  e005              B        |L13.28|
                  |L13.16|
;;;125      }
;;;126      /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
;;;127      else
;;;128      {   
;;;129        FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 
000010  f24301d2          MOV      r1,#0x30d2
000014  f04f4220          MOV      r2,#0xa0000000
000018  f8421020          STR      r1,[r2,r0,LSL #2]
                  |L13.28|
;;;130      }
;;;131      FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
00001c  f06f4270          MVN      r2,#0xf0000000
000020  1c41              ADDS     r1,r0,#1
000022  f04f4320          MOV      r3,#0xa0000000
000026  f8432021          STR      r2,[r3,r1,LSL #2]
;;;132      FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  
00002a  4611              MOV      r1,r2
00002c  461a              MOV      r2,r3
00002e  eb020280          ADD      r2,r2,r0,LSL #2
000032  f8c21104          STR      r1,[r2,#0x104]
;;;133    }
000036  4770              BX       lr
;;;134    
                          ENDP


                          AREA ||i.FSMC_NORSRAMInit||, CODE, READONLY, ALIGN=1

                  FSMC_NORSRAMInit PROC
;;;142      */
;;;143    void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
000000  e9d01201          LDRD     r1,r2,[r0,#4]
;;;144    { 
;;;145      /* Check the parameters */
;;;146      assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
;;;147      assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
;;;148      assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
;;;149      assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
;;;150      assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
;;;151      assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
;;;152      assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
;;;153      assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
;;;154      assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
;;;155      assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
;;;156      assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
;;;157      assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
;;;158      assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  
;;;159      assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
;;;160      assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
;;;161      assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
;;;162      assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
;;;163      assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
;;;164      assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
;;;165      assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 
;;;166      
;;;167      /* Bank1 NOR/SRAM control register configuration */ 
;;;168      FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
000004  4311              ORRS     r1,r1,r2
000006  68c2              LDR      r2,[r0,#0xc]
000008  4311              ORRS     r1,r1,r2
00000a  6902              LDR      r2,[r0,#0x10]
00000c  4311              ORRS     r1,r1,r2
00000e  6942              LDR      r2,[r0,#0x14]
000010  4311              ORRS     r1,r1,r2
000012  6982              LDR      r2,[r0,#0x18]
000014  4311              ORRS     r1,r1,r2
000016  69c2              LDR      r2,[r0,#0x1c]
000018  4311              ORRS     r1,r1,r2
00001a  6a02              LDR      r2,[r0,#0x20]
00001c  4311              ORRS     r1,r1,r2
00001e  6a42              LDR      r2,[r0,#0x24]
000020  4311              ORRS     r1,r1,r2
000022  6a82              LDR      r2,[r0,#0x28]
000024  4311              ORRS     r1,r1,r2
000026  6ac2              LDR      r2,[r0,#0x2c]
000028  4311              ORRS     r1,r1,r2
00002a  6b02              LDR      r2,[r0,#0x30]
00002c  4311              ORRS     r1,r1,r2
00002e  f04f4320          MOV      r3,#0xa0000000
000032  6802              LDR      r2,[r0,#0]
000034  f8431022          STR      r1,[r3,r2,LSL #2]
;;;169                (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
;;;170                FSMC_NORSRAMInitStruct->FSMC_MemoryType |
;;;171                FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
;;;172                FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
;;;173                FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
;;;174                FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
;;;175                FSMC_NORSRAMInitStruct->FSMC_WrapMode |
;;;176                FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
;;;177                FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
;;;178                FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
;;;179                FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
;;;180                FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
;;;181      if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
000038  6881              LDR      r1,[r0,#8]
00003a  2908              CMP      r1,#8
00003c  d108              BNE      |L14.80|
;;;182      {
;;;183        FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
00003e  461a              MOV      r2,r3
000040  6801              LDR      r1,[r0,#0]
000042  f8521021          LDR      r1,[r2,r1,LSL #2]
000046  f0410140          ORR      r1,r1,#0x40
00004a  6802              LDR      r2,[r0,#0]
00004c  f8431022          STR      r1,[r3,r2,LSL #2]
                  |L14.80|
;;;184      }
;;;185      /* Bank1 NOR/SRAM timing register configuration */
;;;186      FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = 
000050  6b41              LDR      r1,[r0,#0x34]
000052  6809              LDR      r1,[r1,#0]
000054  6b42              LDR      r2,[r0,#0x34]
000056  6852              LDR      r2,[r2,#4]
000058  ea411102          ORR      r1,r1,r2,LSL #4
00005c  6b42              LDR      r2,[r0,#0x34]
00005e  6892              LDR      r2,[r2,#8]
000060  ea412102          ORR      r1,r1,r2,LSL #8
000064  6b42              LDR      r2,[r0,#0x34]
000066  68d2              LDR      r2,[r2,#0xc]
000068  ea414102          ORR      r1,r1,r2,LSL #16
00006c  6b42              LDR      r2,[r0,#0x34]
00006e  6912              LDR      r2,[r2,#0x10]
000070  ea415102          ORR      r1,r1,r2,LSL #20
000074  6b42              LDR      r2,[r0,#0x34]
000076  6952              LDR      r2,[r2,#0x14]
000078  ea416102          ORR      r1,r1,r2,LSL #24
00007c  6b42              LDR      r2,[r0,#0x34]
00007e  6992              LDR      r2,[r2,#0x18]
000080  4311              ORRS     r1,r1,r2
000082  6802              LDR      r2,[r0,#0]
000084  1c52              ADDS     r2,r2,#1
000086  f04f4320          MOV      r3,#0xa0000000
00008a  f8431022          STR      r1,[r3,r2,LSL #2]
;;;187                (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
;;;188                (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
;;;189                (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
;;;190                (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
;;;191                (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
;;;192                (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
;;;193                 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
;;;194                
;;;195        
;;;196      /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
;;;197      if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
00008e  6ac1              LDR      r1,[r0,#0x2c]
000090  f5b14f80          CMP      r1,#0x4000
000094  d11a              BNE      |L14.204|
;;;198      {
;;;199        assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
;;;200        assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
;;;201        assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
;;;202        assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
;;;203        assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
;;;204        assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
;;;205        FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
000096  6b81              LDR      r1,[r0,#0x38]
000098  6809              LDR      r1,[r1,#0]
00009a  6b82              LDR      r2,[r0,#0x38]
00009c  6852              LDR      r2,[r2,#4]
00009e  ea411102          ORR      r1,r1,r2,LSL #4
0000a2  6b82              LDR      r2,[r0,#0x38]
0000a4  6892              LDR      r2,[r2,#8]
0000a6  ea412102          ORR      r1,r1,r2,LSL #8
0000aa  6b82              LDR      r2,[r0,#0x38]
0000ac  6912              LDR      r2,[r2,#0x10]
0000ae  ea415102          ORR      r1,r1,r2,LSL #20
0000b2  6b82              LDR      r2,[r0,#0x38]
0000b4  6952              LDR      r2,[r2,#0x14]
0000b6  ea416102          ORR      r1,r1,r2,LSL #24
0000ba  6b82              LDR      r2,[r0,#0x38]
0000bc  6992              LDR      r2,[r2,#0x18]
0000be  4311              ORRS     r1,r1,r2
0000c0  6802              LDR      r2,[r0,#0]
0000c2  eb030282          ADD      r2,r3,r2,LSL #2
0000c6  f8c21104          STR      r1,[r2,#0x104]
0000ca  e008              B        |L14.222|
                  |L14.204|
;;;206                  (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
;;;207                  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
;;;208                  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
;;;209                  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
;;;210                  (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
;;;211                   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
;;;212      }
;;;213      else
;;;214      {
;;;215        FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
0000cc  f06f4170          MVN      r1,#0xf0000000
0000d0  f04f4320          MOV      r3,#0xa0000000
0000d4  6802              LDR      r2,[r0,#0]
0000d6  eb030282          ADD      r2,r3,r2,LSL #2
0000da  f8c21104          STR      r1,[r2,#0x104]
                  |L14.222|
;;;216      }
;;;217    }
0000de  4770              BX       lr
;;;218    
                          ENDP


                          AREA ||i.FSMC_NORSRAMStructInit||, CODE, READONLY, ALIGN=1

                  FSMC_NORSRAMStructInit PROC
;;;224      */
;;;225    void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
000000  2100              MOVS     r1,#0
;;;226    {  
;;;227      /* Reset NOR/SRAM Init structure parameters values */
;;;228      FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
000002  6001              STR      r1,[r0,#0]
;;;229      FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
000004  2102              MOVS     r1,#2
000006  6041              STR      r1,[r0,#4]
;;;230      FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
000008  2100              MOVS     r1,#0
00000a  6081              STR      r1,[r0,#8]
;;;231      FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00000c  60c1              STR      r1,[r0,#0xc]
;;;232      FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00000e  6101              STR      r1,[r0,#0x10]
;;;233      FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
000010  6141              STR      r1,[r0,#0x14]
;;;234      FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
000012  6181              STR      r1,[r0,#0x18]
;;;235      FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
000014  61c1              STR      r1,[r0,#0x1c]
;;;236      FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
000016  6201              STR      r1,[r0,#0x20]
;;;237      FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
000018  f44f5180          MOV      r1,#0x1000
00001c  6241              STR      r1,[r0,#0x24]
;;;238      FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
00001e  0049              LSLS     r1,r1,#1
000020  6281              STR      r1,[r0,#0x28]
;;;239      FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
000022  2100              MOVS     r1,#0
000024  62c1              STR      r1,[r0,#0x2c]
;;;240      FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
000026  6301              STR      r1,[r0,#0x30]
;;;241      FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
000028  210f              MOVS     r1,#0xf
00002a  6b42              LDR      r2,[r0,#0x34]
00002c  6011              STR      r1,[r2,#0]
;;;242      FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
00002e  6b42              LDR      r2,[r0,#0x34]
000030  6051              STR      r1,[r2,#4]
;;;243      FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
000032  21ff              MOVS     r1,#0xff
000034  6b42              LDR      r2,[r0,#0x34]
000036  6091              STR      r1,[r2,#8]
;;;244      FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
000038  210f              MOVS     r1,#0xf
00003a  6b42              LDR      r2,[r0,#0x34]
00003c  60d1              STR      r1,[r2,#0xc]
;;;245      FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
00003e  6b42              LDR      r2,[r0,#0x34]
000040  6111              STR      r1,[r2,#0x10]
;;;246      FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
000042  6b42              LDR      r2,[r0,#0x34]
000044  6151              STR      r1,[r2,#0x14]
;;;247      FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; 
000046  2100              MOVS     r1,#0
000048  6b42              LDR      r2,[r0,#0x34]
00004a  6191              STR      r1,[r2,#0x18]
;;;248      FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
00004c  210f              MOVS     r1,#0xf
00004e  6b82              LDR      r2,[r0,#0x38]
000050  6011              STR      r1,[r2,#0]
;;;249      FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
000052  6b82              LDR      r2,[r0,#0x38]
000054  6051              STR      r1,[r2,#4]
;;;250      FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
000056  21ff              MOVS     r1,#0xff
000058  6b82              LDR      r2,[r0,#0x38]
00005a  6091              STR      r1,[r2,#8]
;;;251      FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
00005c  210f              MOVS     r1,#0xf
00005e  6b82              LDR      r2,[r0,#0x38]
000060  60d1              STR      r1,[r2,#0xc]
;;;252      FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
000062  6b82              LDR      r2,[r0,#0x38]
000064  6111              STR      r1,[r2,#0x10]
;;;253      FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
000066  6b82              LDR      r2,[r0,#0x38]
000068  6151              STR      r1,[r2,#0x14]
;;;254      FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
00006a  2100              MOVS     r1,#0
00006c  6b82              LDR      r2,[r0,#0x38]
00006e  6191              STR      r1,[r2,#0x18]
;;;255    }
000070  4770              BX       lr
;;;256    
                          ENDP


                          AREA ||i.FSMC_PCCARDCmd||, CODE, READONLY, ALIGN=2

                  FSMC_PCCARDCmd PROC
;;;701      */
;;;702    void FSMC_PCCARDCmd(FunctionalState NewState)
000000  b140              CBZ      r0,|L16.20|
;;;703    {
;;;704      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;705      
;;;706      if (NewState != DISABLE)
;;;707      {
;;;708        /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
;;;709        FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
000002  4909              LDR      r1,|L16.40|
000004  6809              LDR      r1,[r1,#0]
000006  f0410104          ORR      r1,r1,#4
00000a  f04f4220          MOV      r2,#0xa0000000
00000e  f8c210a0          STR      r1,[r2,#0xa0]
000012  e008              B        |L16.38|
                  |L16.20|
;;;710      }
;;;711      else
;;;712      {
;;;713        /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
;;;714        FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
000014  4904              LDR      r1,|L16.40|
000016  6809              LDR      r1,[r1,#0]
000018  4a04              LDR      r2,|L16.44|
00001a  ea010102          AND      r1,r1,r2
00001e  f04f4220          MOV      r2,#0xa0000000
000022  f8c210a0          STR      r1,[r2,#0xa0]
                  |L16.38|
;;;715      }
;;;716    }
000026  4770              BX       lr
;;;717    /**
                          ENDP

                  |L16.40|
                          DCD      0xa00000a0
                  |L16.44|
                          DCD      0x000ffffb

                          AREA ||i.FSMC_PCCARDDeInit||, CODE, READONLY, ALIGN=2

                  FSMC_PCCARDDeInit PROC
;;;606      */
;;;607    void FSMC_PCCARDDeInit(void)
000000  2018              MOVS     r0,#0x18
;;;608    {
;;;609      /* Set the FSMC_Bank4 registers to their reset values */
;;;610      FSMC_Bank4->PCR4 = 0x00000018; 
000002  4909              LDR      r1,|L17.40|
000004  6008              STR      r0,[r1,#0]
;;;611      FSMC_Bank4->SR4 = 0x00000000;	
000006  f04f0000          MOV      r0,#0
00000a  f04f4120          MOV      r1,#0xa0000000
00000e  f8c100a4          STR      r0,[r1,#0xa4]
;;;612      FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
000012  f04f30fc          MOV      r0,#0xfcfcfcfc
000016  4905              LDR      r1,|L17.44|
000018  6008              STR      r0,[r1,#0]
;;;613      FSMC_Bank4->PATT4 = 0xFCFCFCFC;
00001a  f1010104          ADD      r1,r1,#4
00001e  6008              STR      r0,[r1,#0]
;;;614      FSMC_Bank4->PIO4 = 0xFCFCFCFC;
000020  f1010104          ADD      r1,r1,#4
000024  6008              STR      r0,[r1,#0]
;;;615    }
000026  4770              BX       lr
;;;616    
                          ENDP

                  |L17.40|
                          DCD      0xa00000a0
                  |L17.44|
                          DCD      0xa00000a8

                          AREA ||i.FSMC_PCCARDInit||, CODE, READONLY, ALIGN=2

                  FSMC_PCCARDInit PROC
;;;623      */
;;;624    void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
000000  6801              LDR      r1,[r0,#0]
;;;625    {
;;;626      /* Check the parameters */
;;;627      assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
;;;628      assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
;;;629      assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
;;;630     
;;;631      assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
;;;632      assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
;;;633      assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
;;;634      assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
;;;635      
;;;636      assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
;;;637      assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
;;;638      assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
;;;639      assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
;;;640      assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
;;;641      assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
;;;642      assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
;;;643      assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
;;;644      
;;;645      /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
;;;646      FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
000002  f0410110          ORR      r1,r1,#0x10
000006  6842              LDR      r2,[r0,#4]
000008  ea412142          ORR      r1,r1,r2,LSL #9
00000c  6882              LDR      r2,[r0,#8]
00000e  ea413142          ORR      r1,r1,r2,LSL #13
000012  4a1a              LDR      r2,|L18.124|
000014  6011              STR      r1,[r2,#0]
;;;647                         FSMC_MemoryDataWidth_16b |  
;;;648                         (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
;;;649                         (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
;;;650                
;;;651      /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
;;;652      FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
000016  68c1              LDR      r1,[r0,#0xc]
000018  6809              LDR      r1,[r1,#0]
00001a  68c2              LDR      r2,[r0,#0xc]
00001c  6852              LDR      r2,[r2,#4]
00001e  ea412102          ORR      r1,r1,r2,LSL #8
000022  68c2              LDR      r2,[r0,#0xc]
000024  6892              LDR      r2,[r2,#8]
000026  ea414102          ORR      r1,r1,r2,LSL #16
00002a  68c2              LDR      r2,[r0,#0xc]
00002c  68d2              LDR      r2,[r2,#0xc]
00002e  ea416102          ORR      r1,r1,r2,LSL #24
000032  4a13              LDR      r2,|L18.128|
000034  6011              STR      r1,[r2,#0]
;;;653                          (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;654                          (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;655                          (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
;;;656                
;;;657      /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
;;;658      FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
000036  6901              LDR      r1,[r0,#0x10]
000038  6809              LDR      r1,[r1,#0]
00003a  6902              LDR      r2,[r0,#0x10]
00003c  6852              LDR      r2,[r2,#4]
00003e  ea412102          ORR      r1,r1,r2,LSL #8
000042  6902              LDR      r2,[r0,#0x10]
000044  6892              LDR      r2,[r2,#8]
000046  ea414102          ORR      r1,r1,r2,LSL #16
00004a  6902              LDR      r2,[r0,#0x10]
00004c  68d2              LDR      r2,[r2,#0xc]
00004e  ea416102          ORR      r1,r1,r2,LSL #24
000052  4a0c              LDR      r2,|L18.132|
000054  6011              STR      r1,[r2,#0]
;;;659                          (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;660                          (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;661                          (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);	
;;;662                
;;;663      /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
;;;664      FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
000056  6941              LDR      r1,[r0,#0x14]
000058  6809              LDR      r1,[r1,#0]
00005a  6942              LDR      r2,[r0,#0x14]
00005c  6852              LDR      r2,[r2,#4]
00005e  ea412102          ORR      r1,r1,r2,LSL #8
000062  6942              LDR      r2,[r0,#0x14]
000064  6892              LDR      r2,[r2,#8]
000066  ea414102          ORR      r1,r1,r2,LSL #16
00006a  6942              LDR      r2,[r0,#0x14]
00006c  68d2              LDR      r2,[r2,#0xc]
00006e  ea416102          ORR      r1,r1,r2,LSL #24
000072  f04f4220          MOV      r2,#0xa0000000
000076  f8c210b0          STR      r1,[r2,#0xb0]
;;;665                         (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;666                         (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;667                         (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             
;;;668    }
00007a  4770              BX       lr
;;;669    
                          ENDP

                  |L18.124|
                          DCD      0xa00000a0
                  |L18.128|
                          DCD      0xa00000a8
                  |L18.132|
                          DCD      0xa00000ac

                          AREA ||i.FSMC_PCCARDStructInit||, CODE, READONLY, ALIGN=1

                  FSMC_PCCARDStructInit PROC
;;;675      */
;;;676    void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
000000  2100              MOVS     r1,#0
;;;677    {
;;;678      /* Reset PCCARD Init structure parameters values */
;;;679      FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
000002  6001              STR      r1,[r0,#0]
;;;680      FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
000004  6041              STR      r1,[r0,#4]
;;;681      FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
000006  6081              STR      r1,[r0,#8]
;;;682      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000008  21fc              MOVS     r1,#0xfc
00000a  68c2              LDR      r2,[r0,#0xc]
00000c  6011              STR      r1,[r2,#0]
;;;683      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00000e  68c2              LDR      r2,[r0,#0xc]
000010  6051              STR      r1,[r2,#4]
;;;684      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000012  68c2              LDR      r2,[r0,#0xc]
000014  6091              STR      r1,[r2,#8]
;;;685      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000016  68c2              LDR      r2,[r0,#0xc]
000018  60d1              STR      r1,[r2,#0xc]
;;;686      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00001a  6902              LDR      r2,[r0,#0x10]
00001c  6011              STR      r1,[r2,#0]
;;;687      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00001e  6902              LDR      r2,[r0,#0x10]
000020  6051              STR      r1,[r2,#4]
;;;688      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000022  6902              LDR      r2,[r0,#0x10]
000024  6091              STR      r1,[r2,#8]
;;;689      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	
000026  6902              LDR      r2,[r0,#0x10]
000028  60d1              STR      r1,[r2,#0xc]
;;;690      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00002a  6942              LDR      r2,[r0,#0x14]
00002c  6011              STR      r1,[r2,#0]
;;;691      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00002e  6942              LDR      r2,[r0,#0x14]
000030  6051              STR      r1,[r2,#4]
;;;692      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000032  6942              LDR      r2,[r0,#0x14]
000034  6091              STR      r1,[r2,#8]
;;;693      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000036  6942              LDR      r2,[r0,#0x14]
000038  60d1              STR      r1,[r2,#0xc]
;;;694    }
00003a  4770              BX       lr
;;;695    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_fsmc.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___16_stm32f4xx_fsmc_c_2e710976____REV16|
#line 114 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___16_stm32f4xx_fsmc_c_2e710976____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___16_stm32f4xx_fsmc_c_2e710976____REVSH|
#line 128
|__asm___16_stm32f4xx_fsmc_c_2e710976____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
