; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\STM324xG_EVAL\stm32f4xx_dma.o --asm_dir=.\STM324xG_EVAL\ --list_dir=.\STM324xG_EVAL\ --depend=.\STM324xG_EVAL\stm32f4xx_dma.d --cpu=Cortex-M4.fp --apcs=interwork -O0 -Otime -I..\ -I..\..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\..\Utilities\STM32_EVAL\Common -I..\..\..\Utilities\STM32_EVAL\STM3240_41_G_EVAL -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F4xx -D__MICROLIB -DUSE_STM324xG_EVAL -DSTM32F4XX -DUSE_STDPERIPH_DRIVER --omf_browse=.\STM324xG_EVAL\stm32f4xx_dma.crf ..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dma.c]
                          THUMB

                          AREA ||i.DMA_ClearFlag||, CODE, READONLY, ALIGN=2

                  DMA_ClearFlag PROC
;;;1052     */
;;;1053   void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
000000  4602              MOV      r2,r0
;;;1054   {
;;;1055     DMA_TypeDef* DMAy;
;;;1056   
;;;1057     /* Check the parameters */
;;;1058     assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;1059     assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
;;;1060   
;;;1061     /* Determine the DMA to which belongs the stream */
;;;1062     if (DMAy_Streamx < DMA2_Stream0)
000002  4b09              LDR      r3,|L1.40|
000004  429a              CMP      r2,r3
000006  d201              BCS      |L1.12|
;;;1063     {
;;;1064       /* DMAy_Streamx belongs to DMA1 */
;;;1065       DMAy = DMA1; 
000008  4808              LDR      r0,|L1.44|
00000a  e001              B        |L1.16|
                  |L1.12|
;;;1066     } 
;;;1067     else 
;;;1068     {
;;;1069       /* DMAy_Streamx belongs to DMA2 */
;;;1070       DMAy = DMA2; 
00000c  4806              LDR      r0,|L1.40|
00000e  3810              SUBS     r0,r0,#0x10
                  |L1.16|
;;;1071     }
;;;1072   
;;;1073     /* Check if LIFCR or HIFCR register is targeted */
;;;1074     if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
000010  f0115f00          TST      r1,#0x20000000
000014  d003              BEQ      |L1.30|
;;;1075     {
;;;1076       /* Set DMAy HIFCR register clear flag bits */
;;;1077       DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
000016  4b06              LDR      r3,|L1.48|
000018  400b              ANDS     r3,r3,r1
00001a  60c3              STR      r3,[r0,#0xc]
00001c  e002              B        |L1.36|
                  |L1.30|
;;;1078     }
;;;1079     else 
;;;1080     {
;;;1081       /* Set DMAy LIFCR register clear flag bits */
;;;1082       DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
00001e  4b04              LDR      r3,|L1.48|
000020  400b              ANDS     r3,r3,r1
000022  6083              STR      r3,[r0,#8]
                  |L1.36|
;;;1083     }    
;;;1084   }
000024  4770              BX       lr
;;;1085   
                          ENDP

000026  0000              DCW      0x0000
                  |L1.40|
                          DCD      0x40026410
                  |L1.44|
                          DCD      0x40026000
                  |L1.48|
                          DCD      0x0f7d0f7d

                          AREA ||i.DMA_ClearITPendingBit||, CODE, READONLY, ALIGN=2

                  DMA_ClearITPendingBit PROC
;;;1233     */
;;;1234   void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
000000  4602              MOV      r2,r0
;;;1235   {
;;;1236     DMA_TypeDef* DMAy;
;;;1237   
;;;1238     /* Check the parameters */
;;;1239     assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;1240     assert_param(IS_DMA_CLEAR_IT(DMA_IT));
;;;1241   
;;;1242     /* Determine the DMA to which belongs the stream */
;;;1243     if (DMAy_Streamx < DMA2_Stream0)
000002  4b09              LDR      r3,|L2.40|
000004  429a              CMP      r2,r3
000006  d201              BCS      |L2.12|
;;;1244     {
;;;1245       /* DMAy_Streamx belongs to DMA1 */
;;;1246       DMAy = DMA1; 
000008  4808              LDR      r0,|L2.44|
00000a  e001              B        |L2.16|
                  |L2.12|
;;;1247     } 
;;;1248     else 
;;;1249     {
;;;1250       /* DMAy_Streamx belongs to DMA2 */
;;;1251       DMAy = DMA2; 
00000c  4806              LDR      r0,|L2.40|
00000e  3810              SUBS     r0,r0,#0x10
                  |L2.16|
;;;1252     }
;;;1253   
;;;1254     /* Check if LIFCR or HIFCR register is targeted */
;;;1255     if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
000010  f0115f00          TST      r1,#0x20000000
000014  d003              BEQ      |L2.30|
;;;1256     {
;;;1257       /* Set DMAy HIFCR register clear interrupt bits */
;;;1258       DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
000016  4b06              LDR      r3,|L2.48|
000018  400b              ANDS     r3,r3,r1
00001a  60c3              STR      r3,[r0,#0xc]
00001c  e002              B        |L2.36|
                  |L2.30|
;;;1259     }
;;;1260     else 
;;;1261     {
;;;1262       /* Set DMAy LIFCR register clear interrupt bits */
;;;1263       DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
00001e  4b04              LDR      r3,|L2.48|
000020  400b              ANDS     r3,r3,r1
000022  6083              STR      r3,[r0,#8]
                  |L2.36|
;;;1264     }   
;;;1265   }
000024  4770              BX       lr
;;;1266   
                          ENDP

000026  0000              DCW      0x0000
                  |L2.40|
                          DCD      0x40026410
                  |L2.44|
                          DCD      0x40026000
                  |L2.48|
                          DCD      0x0f7d0f7d

                          AREA ||i.DMA_Cmd||, CODE, READONLY, ALIGN=1

                  DMA_Cmd PROC
;;;469      */
;;;470    void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
000000  b121              CBZ      r1,|L3.12|
;;;471    {
;;;472      /* Check the parameters */
;;;473      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;474      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;475    
;;;476      if (NewState != DISABLE)
;;;477      {
;;;478        /* Enable the selected DMAy Streamx by setting EN bit */
;;;479        DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN;
000002  6802              LDR      r2,[r0,#0]
000004  f0420201          ORR      r2,r2,#1
000008  6002              STR      r2,[r0,#0]
00000a  e003              B        |L3.20|
                  |L3.12|
;;;480      }
;;;481      else
;;;482      {
;;;483        /* Disable the selected DMAy Streamx by clearing EN bit */
;;;484        DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN;
00000c  6802              LDR      r2,[r0,#0]
00000e  f0220201          BIC      r2,r2,#1
000012  6002              STR      r2,[r0,#0]
                  |L3.20|
;;;485      }
;;;486    }
000014  4770              BX       lr
;;;487    
                          ENDP


                          AREA ||i.DMA_DeInit||, CODE, READONLY, ALIGN=2

                  DMA_DeInit PROC
;;;187      */
;;;188    void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx)
000000  6801              LDR      r1,[r0,#0]
;;;189    {
;;;190      /* Check the parameters */
;;;191      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;192    
;;;193      /* Disable the selected DMAy Streamx */
;;;194      DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN);
000002  f0210101          BIC      r1,r1,#1
000006  6001              STR      r1,[r0,#0]
;;;195    
;;;196      /* Reset DMAy Streamx control register */
;;;197      DMAy_Streamx->CR  = 0;
000008  2100              MOVS     r1,#0
00000a  6001              STR      r1,[r0,#0]
;;;198      
;;;199      /* Reset DMAy Streamx Number of Data to Transfer register */
;;;200      DMAy_Streamx->NDTR = 0;
00000c  6041              STR      r1,[r0,#4]
;;;201      
;;;202      /* Reset DMAy Streamx peripheral address register */
;;;203      DMAy_Streamx->PAR  = 0;
00000e  6081              STR      r1,[r0,#8]
;;;204      
;;;205      /* Reset DMAy Streamx memory 0 address register */
;;;206      DMAy_Streamx->M0AR = 0;
000010  60c1              STR      r1,[r0,#0xc]
;;;207    
;;;208      /* Reset DMAy Streamx memory 1 address register */
;;;209      DMAy_Streamx->M1AR = 0;
000012  6101              STR      r1,[r0,#0x10]
;;;210    
;;;211      /* Reset DMAy Streamx FIFO control register */
;;;212      DMAy_Streamx->FCR = (uint32_t)0x00000021; 
000014  2121              MOVS     r1,#0x21
000016  6141              STR      r1,[r0,#0x14]
;;;213    
;;;214      /* Reset interrupt pending bits for the selected stream */
;;;215      if (DMAy_Streamx == DMA1_Stream0)
000018  494a              LDR      r1,|L4.324|
00001a  4288              CMP      r0,r1
00001c  d104              BNE      |L4.40|
;;;216      {
;;;217        /* Reset interrupt pending bits for DMA1 Stream0 */
;;;218        DMA1->LIFCR = DMA_Stream0_IT_MASK;
00001e  213d              MOVS     r1,#0x3d
000020  4a48              LDR      r2,|L4.324|
000022  3a10              SUBS     r2,r2,#0x10
000024  6091              STR      r1,[r2,#8]
000026  e08c              B        |L4.322|
                  |L4.40|
;;;219      }
;;;220      else if (DMAy_Streamx == DMA1_Stream1)
000028  4946              LDR      r1,|L4.324|
00002a  3118              ADDS     r1,r1,#0x18
00002c  4288              CMP      r0,r1
00002e  d105              BNE      |L4.60|
;;;221      {
;;;222        /* Reset interrupt pending bits for DMA1 Stream1 */
;;;223        DMA1->LIFCR = DMA_Stream1_IT_MASK;
000030  f44f6174          MOV      r1,#0xf40
000034  4a43              LDR      r2,|L4.324|
000036  3a10              SUBS     r2,r2,#0x10
000038  6091              STR      r1,[r2,#8]
00003a  e082              B        |L4.322|
                  |L4.60|
;;;224      }
;;;225      else if (DMAy_Streamx == DMA1_Stream2)
00003c  4941              LDR      r1,|L4.324|
00003e  3130              ADDS     r1,r1,#0x30
000040  4288              CMP      r0,r1
000042  d105              BNE      |L4.80|
;;;226      {
;;;227        /* Reset interrupt pending bits for DMA1 Stream2 */
;;;228        DMA1->LIFCR = DMA_Stream2_IT_MASK;
000044  f44f1174          MOV      r1,#0x3d0000
000048  4a3e              LDR      r2,|L4.324|
00004a  3a10              SUBS     r2,r2,#0x10
00004c  6091              STR      r1,[r2,#8]
00004e  e078              B        |L4.322|
                  |L4.80|
;;;229      }
;;;230      else if (DMAy_Streamx == DMA1_Stream3)
000050  493c              LDR      r1,|L4.324|
000052  3148              ADDS     r1,r1,#0x48
000054  4288              CMP      r0,r1
000056  d105              BNE      |L4.100|
;;;231      {
;;;232        /* Reset interrupt pending bits for DMA1 Stream3 */
;;;233        DMA1->LIFCR = DMA_Stream3_IT_MASK;
000058  f04f6174          MOV      r1,#0xf400000
00005c  4a39              LDR      r2,|L4.324|
00005e  3a10              SUBS     r2,r2,#0x10
000060  6091              STR      r1,[r2,#8]
000062  e06e              B        |L4.322|
                  |L4.100|
;;;234      }
;;;235      else if (DMAy_Streamx == DMA1_Stream4)
000064  4937              LDR      r1,|L4.324|
000066  3160              ADDS     r1,r1,#0x60
000068  4288              CMP      r0,r1
00006a  d104              BNE      |L4.118|
;;;236      {
;;;237        /* Reset interrupt pending bits for DMA1 Stream4 */
;;;238        DMA1->HIFCR = DMA_Stream4_IT_MASK;
00006c  4936              LDR      r1,|L4.328|
00006e  4a35              LDR      r2,|L4.324|
000070  3a10              SUBS     r2,r2,#0x10
000072  60d1              STR      r1,[r2,#0xc]
000074  e065              B        |L4.322|
                  |L4.118|
;;;239      }
;;;240      else if (DMAy_Streamx == DMA1_Stream5)
000076  4933              LDR      r1,|L4.324|
000078  3178              ADDS     r1,r1,#0x78
00007a  4288              CMP      r0,r1
00007c  d104              BNE      |L4.136|
;;;241      {
;;;242        /* Reset interrupt pending bits for DMA1 Stream5 */
;;;243        DMA1->HIFCR = DMA_Stream5_IT_MASK;
00007e  4933              LDR      r1,|L4.332|
000080  4a30              LDR      r2,|L4.324|
000082  3a10              SUBS     r2,r2,#0x10
000084  60d1              STR      r1,[r2,#0xc]
000086  e05c              B        |L4.322|
                  |L4.136|
;;;244      }
;;;245      else if (DMAy_Streamx == DMA1_Stream6)
000088  492e              LDR      r1,|L4.324|
00008a  3190              ADDS     r1,r1,#0x90
00008c  4288              CMP      r0,r1
00008e  d104              BNE      |L4.154|
;;;246      {
;;;247        /* Reset interrupt pending bits for DMA1 Stream6 */
;;;248        DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
000090  492f              LDR      r1,|L4.336|
000092  4a2c              LDR      r2,|L4.324|
000094  3a10              SUBS     r2,r2,#0x10
000096  60d1              STR      r1,[r2,#0xc]
000098  e053              B        |L4.322|
                  |L4.154|
;;;249      }
;;;250      else if (DMAy_Streamx == DMA1_Stream7)
00009a  492a              LDR      r1,|L4.324|
00009c  31a8              ADDS     r1,r1,#0xa8
00009e  4288              CMP      r0,r1
0000a0  d105              BNE      |L4.174|
;;;251      {
;;;252        /* Reset interrupt pending bits for DMA1 Stream7 */
;;;253        DMA1->HIFCR = DMA_Stream7_IT_MASK;
0000a2  f04f513d          MOV      r1,#0x2f400000
0000a6  4a27              LDR      r2,|L4.324|
0000a8  3a10              SUBS     r2,r2,#0x10
0000aa  60d1              STR      r1,[r2,#0xc]
0000ac  e049              B        |L4.322|
                  |L4.174|
;;;254      }
;;;255      else if (DMAy_Streamx == DMA2_Stream0)
0000ae  4929              LDR      r1,|L4.340|
0000b0  4288              CMP      r0,r1
0000b2  d104              BNE      |L4.190|
;;;256      {
;;;257        /* Reset interrupt pending bits for DMA2 Stream0 */
;;;258        DMA2->LIFCR = DMA_Stream0_IT_MASK;
0000b4  213d              MOVS     r1,#0x3d
0000b6  4a27              LDR      r2,|L4.340|
0000b8  3a08              SUBS     r2,r2,#8
0000ba  6011              STR      r1,[r2,#0]
0000bc  e041              B        |L4.322|
                  |L4.190|
;;;259      }
;;;260      else if (DMAy_Streamx == DMA2_Stream1)
0000be  4925              LDR      r1,|L4.340|
0000c0  3118              ADDS     r1,r1,#0x18
0000c2  4288              CMP      r0,r1
0000c4  d105              BNE      |L4.210|
;;;261      {
;;;262        /* Reset interrupt pending bits for DMA2 Stream1 */
;;;263        DMA2->LIFCR = DMA_Stream1_IT_MASK;
0000c6  f44f6174          MOV      r1,#0xf40
0000ca  4a22              LDR      r2,|L4.340|
0000cc  3a08              SUBS     r2,r2,#8
0000ce  6011              STR      r1,[r2,#0]
0000d0  e037              B        |L4.322|
                  |L4.210|
;;;264      }
;;;265      else if (DMAy_Streamx == DMA2_Stream2)
0000d2  4920              LDR      r1,|L4.340|
0000d4  3130              ADDS     r1,r1,#0x30
0000d6  4288              CMP      r0,r1
0000d8  d105              BNE      |L4.230|
;;;266      {
;;;267        /* Reset interrupt pending bits for DMA2 Stream2 */
;;;268        DMA2->LIFCR = DMA_Stream2_IT_MASK;
0000da  f44f1174          MOV      r1,#0x3d0000
0000de  4a1d              LDR      r2,|L4.340|
0000e0  3a08              SUBS     r2,r2,#8
0000e2  6011              STR      r1,[r2,#0]
0000e4  e02d              B        |L4.322|
                  |L4.230|
;;;269      }
;;;270      else if (DMAy_Streamx == DMA2_Stream3)
0000e6  491b              LDR      r1,|L4.340|
0000e8  3148              ADDS     r1,r1,#0x48
0000ea  4288              CMP      r0,r1
0000ec  d105              BNE      |L4.250|
;;;271      {
;;;272        /* Reset interrupt pending bits for DMA2 Stream3 */
;;;273        DMA2->LIFCR = DMA_Stream3_IT_MASK;
0000ee  f04f6174          MOV      r1,#0xf400000
0000f2  4a18              LDR      r2,|L4.340|
0000f4  3a08              SUBS     r2,r2,#8
0000f6  6011              STR      r1,[r2,#0]
0000f8  e023              B        |L4.322|
                  |L4.250|
;;;274      }
;;;275      else if (DMAy_Streamx == DMA2_Stream4)
0000fa  4916              LDR      r1,|L4.340|
0000fc  3160              ADDS     r1,r1,#0x60
0000fe  4288              CMP      r0,r1
000100  d104              BNE      |L4.268|
;;;276      {
;;;277        /* Reset interrupt pending bits for DMA2 Stream4 */
;;;278        DMA2->HIFCR = DMA_Stream4_IT_MASK;
000102  4911              LDR      r1,|L4.328|
000104  4a13              LDR      r2,|L4.340|
000106  1f12              SUBS     r2,r2,#4
000108  6011              STR      r1,[r2,#0]
00010a  e01a              B        |L4.322|
                  |L4.268|
;;;279      }
;;;280      else if (DMAy_Streamx == DMA2_Stream5)
00010c  4911              LDR      r1,|L4.340|
00010e  3178              ADDS     r1,r1,#0x78
000110  4288              CMP      r0,r1
000112  d104              BNE      |L4.286|
;;;281      {
;;;282        /* Reset interrupt pending bits for DMA2 Stream5 */
;;;283        DMA2->HIFCR = DMA_Stream5_IT_MASK;
000114  490d              LDR      r1,|L4.332|
000116  4a0f              LDR      r2,|L4.340|
000118  1f12              SUBS     r2,r2,#4
00011a  6011              STR      r1,[r2,#0]
00011c  e011              B        |L4.322|
                  |L4.286|
;;;284      }
;;;285      else if (DMAy_Streamx == DMA2_Stream6)
00011e  490d              LDR      r1,|L4.340|
000120  3190              ADDS     r1,r1,#0x90
000122  4288              CMP      r0,r1
000124  d104              BNE      |L4.304|
;;;286      {
;;;287        /* Reset interrupt pending bits for DMA2 Stream6 */
;;;288        DMA2->HIFCR = DMA_Stream6_IT_MASK;
000126  490a              LDR      r1,|L4.336|
000128  4a0a              LDR      r2,|L4.340|
00012a  1f12              SUBS     r2,r2,#4
00012c  6011              STR      r1,[r2,#0]
00012e  e008              B        |L4.322|
                  |L4.304|
;;;289      }
;;;290      else 
;;;291      {
;;;292        if (DMAy_Streamx == DMA2_Stream7)
000130  4908              LDR      r1,|L4.340|
000132  31a8              ADDS     r1,r1,#0xa8
000134  4288              CMP      r0,r1
000136  d104              BNE      |L4.322|
;;;293        {
;;;294          /* Reset interrupt pending bits for DMA2 Stream7 */
;;;295          DMA2->HIFCR = DMA_Stream7_IT_MASK;
000138  f04f513d          MOV      r1,#0x2f400000
00013c  4a05              LDR      r2,|L4.340|
00013e  1f12              SUBS     r2,r2,#4
000140  6011              STR      r1,[r2,#0]
                  |L4.322|
;;;296        }
;;;297      }
;;;298    }
000142  4770              BX       lr
;;;299    
                          ENDP

                  |L4.324|
                          DCD      0x40026010
                  |L4.328|
                          DCD      0x2000003d
                  |L4.332|
                          DCD      0x20000f40
                  |L4.336|
                          DCD      0x203d0000
                  |L4.340|
                          DCD      0x40026410

                          AREA ||i.DMA_DoubleBufferModeCmd||, CODE, READONLY, ALIGN=1

                  DMA_DoubleBufferModeCmd PROC
;;;748      */
;;;749    void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
000000  b121              CBZ      r1,|L5.12|
;;;750    {  
;;;751      /* Check the parameters */
;;;752      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;753      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;754    
;;;755      /* Configure the Double Buffer mode */
;;;756      if (NewState != DISABLE)
;;;757      {
;;;758        /* Enable the Double buffer mode */
;;;759        DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM;
000002  6802              LDR      r2,[r0,#0]
000004  f4422280          ORR      r2,r2,#0x40000
000008  6002              STR      r2,[r0,#0]
00000a  e003              B        |L5.20|
                  |L5.12|
;;;760      }
;;;761      else
;;;762      {
;;;763        /* Disable the Double buffer mode */
;;;764        DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM;
00000c  6802              LDR      r2,[r0,#0]
00000e  f4222280          BIC      r2,r2,#0x40000
000012  6002              STR      r2,[r0,#0]
                  |L5.20|
;;;765      }
;;;766    }
000014  4770              BX       lr
;;;767    
                          ENDP


                          AREA ||i.DMA_DoubleBufferModeConfig||, CODE, READONLY, ALIGN=1

                  DMA_DoubleBufferModeConfig PROC
;;;717      */
;;;718    void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
000000  b122              CBZ      r2,|L6.12|
;;;719                                    uint32_t DMA_CurrentMemory)
;;;720    {  
;;;721      /* Check the parameters */
;;;722      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;723      assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
;;;724    
;;;725      if (DMA_CurrentMemory != DMA_Memory_0)
;;;726      {
;;;727        /* Set Memory 1 as current memory address */
;;;728        DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT);    
000002  6803              LDR      r3,[r0,#0]
000004  f4432300          ORR      r3,r3,#0x80000
000008  6003              STR      r3,[r0,#0]
00000a  e003              B        |L6.20|
                  |L6.12|
;;;729      }
;;;730      else
;;;731      {
;;;732        /* Set Memory 0 as current memory address */
;;;733        DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT);    
00000c  6803              LDR      r3,[r0,#0]
00000e  f4232300          BIC      r3,r3,#0x80000
000012  6003              STR      r3,[r0,#0]
                  |L6.20|
;;;734      }
;;;735    
;;;736      /* Write to DMAy Streamx M1AR */
;;;737      DMAy_Streamx->M1AR = Memory1BaseAddr;
000014  6101              STR      r1,[r0,#0x10]
;;;738    }
000016  4770              BX       lr
;;;739    
                          ENDP


                          AREA ||i.DMA_FlowControllerConfig||, CODE, READONLY, ALIGN=1

                  DMA_FlowControllerConfig PROC
;;;541      */
;;;542    void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl)
000000  b121              CBZ      r1,|L7.12|
;;;543    {
;;;544      /* Check the parameters */
;;;545      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;546      assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
;;;547    
;;;548      /* Check the needed flow controller  */
;;;549      if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
;;;550      {
;;;551        /* Configure DMA_SxCR_PFCTRL bit with the input parameter */
;;;552        DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL;   
000002  6802              LDR      r2,[r0,#0]
000004  f0420220          ORR      r2,r2,#0x20
000008  6002              STR      r2,[r0,#0]
00000a  e003              B        |L7.20|
                  |L7.12|
;;;553      }
;;;554      else
;;;555      {
;;;556        /* Clear the PFCTRL bit: Memory is the flow controller */
;;;557        DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL;    
00000c  6802              LDR      r2,[r0,#0]
00000e  f0220220          BIC      r2,r2,#0x20
000012  6002              STR      r2,[r0,#0]
                  |L7.20|
;;;558      }
;;;559    }
000014  4770              BX       lr
;;;560    /**
                          ENDP


                          AREA ||i.DMA_GetCmdStatus||, CODE, READONLY, ALIGN=1

                  DMA_GetCmdStatus PROC
;;;924      */
;;;925    FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx)
000000  4601              MOV      r1,r0
;;;926    {
;;;927      FunctionalState state = DISABLE;
000002  2000              MOVS     r0,#0
;;;928    
;;;929      /* Check the parameters */
;;;930      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;931    
;;;932      if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0)
000004  680a              LDR      r2,[r1,#0]
000006  f0120f01          TST      r2,#1
00000a  d001              BEQ      |L8.16|
;;;933      {
;;;934        /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
;;;935        state = ENABLE;
00000c  2001              MOVS     r0,#1
00000e  e000              B        |L8.18|
                  |L8.16|
;;;936      }
;;;937      else
;;;938      {
;;;939        /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and 
;;;940            all transfers are complete) */
;;;941        state = DISABLE;
000010  2000              MOVS     r0,#0
                  |L8.18|
;;;942      }
;;;943      return state;
;;;944    }
000012  4770              BX       lr
;;;945    
                          ENDP


                          AREA ||i.DMA_GetCurrDataCounter||, CODE, READONLY, ALIGN=1

                  DMA_GetCurrDataCounter PROC
;;;640      */
;;;641    uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)
000000  4601              MOV      r1,r0
;;;642    {
;;;643      /* Check the parameters */
;;;644      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;645    
;;;646      /* Return the number of remaining data units for DMAy Streamx */
;;;647      return ((uint16_t)(DMAy_Streamx->NDTR));
000002  6848              LDR      r0,[r1,#4]
000004  b280              UXTH     r0,r0
;;;648    }
000006  4770              BX       lr
;;;649    /**
                          ENDP


                          AREA ||i.DMA_GetCurrentMemoryTarget||, CODE, READONLY, ALIGN=1

                  DMA_GetCurrentMemoryTarget PROC
;;;815      */
;;;816    uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx)
000000  4601              MOV      r1,r0
;;;817    {
;;;818      uint32_t tmp = 0;
000002  2000              MOVS     r0,#0
;;;819      
;;;820      /* Check the parameters */
;;;821      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;822    
;;;823      /* Get the current memory target */
;;;824      if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0)
000004  680a              LDR      r2,[r1,#0]
000006  f4122f00          TST      r2,#0x80000
00000a  d001              BEQ      |L10.16|
;;;825      {
;;;826        /* Current memory buffer used is Memory 1 */
;;;827        tmp = 1;
00000c  2001              MOVS     r0,#1
00000e  e000              B        |L10.18|
                  |L10.16|
;;;828      }  
;;;829      else
;;;830      {
;;;831        /* Current memory buffer used is Memory 0 */
;;;832        tmp = 0;    
000010  2000              MOVS     r0,#0
                  |L10.18|
;;;833      }
;;;834      return tmp;
;;;835    }
000012  4770              BX       lr
;;;836    /**
                          ENDP


                          AREA ||i.DMA_GetFIFOStatus||, CODE, READONLY, ALIGN=1

                  DMA_GetFIFOStatus PROC
;;;958      */
;;;959    uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)
000000  4601              MOV      r1,r0
;;;960    {
;;;961      uint32_t tmpreg = 0;
000002  2000              MOVS     r0,#0
;;;962     
;;;963      /* Check the parameters */
;;;964      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;965      
;;;966      /* Get the FIFO level bits */
;;;967      tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));
000004  694a              LDR      r2,[r1,#0x14]
000006  f0020038          AND      r0,r2,#0x38
;;;968      
;;;969      return tmpreg;
;;;970    }
00000a  4770              BX       lr
;;;971    
                          ENDP


                          AREA ||i.DMA_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  DMA_GetFlagStatus PROC
;;;985      */
;;;986    FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
000000  b510              PUSH     {r4,lr}
;;;987    {
000002  4603              MOV      r3,r0
000004  460a              MOV      r2,r1
;;;988      FlagStatus bitstatus = RESET;
000006  2000              MOVS     r0,#0
;;;989      DMA_TypeDef* DMAy;
;;;990      uint32_t tmpreg = 0;
000008  4684              MOV      r12,r0
;;;991    
;;;992      /* Check the parameters */
;;;993      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;994      assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
;;;995    
;;;996      /* Determine the DMA to which belongs the stream */
;;;997      if (DMAy_Streamx < DMA2_Stream0)
00000a  4c0c              LDR      r4,|L12.60|
00000c  42a3              CMP      r3,r4
00000e  d201              BCS      |L12.20|
;;;998      {
;;;999        /* DMAy_Streamx belongs to DMA1 */
;;;1000       DMAy = DMA1; 
000010  490b              LDR      r1,|L12.64|
000012  e001              B        |L12.24|
                  |L12.20|
;;;1001     } 
;;;1002     else 
;;;1003     {
;;;1004       /* DMAy_Streamx belongs to DMA2 */
;;;1005       DMAy = DMA2; 
000014  4909              LDR      r1,|L12.60|
000016  3910              SUBS     r1,r1,#0x10
                  |L12.24|
;;;1006     }
;;;1007   
;;;1008     /* Check if the flag is in HISR or LISR */
;;;1009     if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
000018  f0125f00          TST      r2,#0x20000000
00001c  d002              BEQ      |L12.36|
;;;1010     {
;;;1011       /* Get DMAy HISR register value */
;;;1012       tmpreg = DMAy->HISR;
00001e  f8d1c004          LDR      r12,[r1,#4]
000022  e001              B        |L12.40|
                  |L12.36|
;;;1013     }
;;;1014     else
;;;1015     {
;;;1016       /* Get DMAy LISR register value */
;;;1017       tmpreg = DMAy->LISR;
000024  f8d1c000          LDR      r12,[r1,#0]
                  |L12.40|
;;;1018     }   
;;;1019    
;;;1020     /* Mask the reserved bits */
;;;1021     tmpreg &= (uint32_t)RESERVED_MASK;
000028  4c06              LDR      r4,|L12.68|
00002a  ea0c0c04          AND      r12,r12,r4
;;;1022   
;;;1023     /* Check the status of the specified DMA flag */
;;;1024     if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
00002e  ea1c0f02          TST      r12,r2
000032  d001              BEQ      |L12.56|
;;;1025     {
;;;1026       /* DMA_FLAG is set */
;;;1027       bitstatus = SET;
000034  2001              MOVS     r0,#1
000036  e000              B        |L12.58|
                  |L12.56|
;;;1028     }
;;;1029     else
;;;1030     {
;;;1031       /* DMA_FLAG is reset */
;;;1032       bitstatus = RESET;
000038  2000              MOVS     r0,#0
                  |L12.58|
;;;1033     }
;;;1034   
;;;1035     /* Return the DMA_FLAG status */
;;;1036     return  bitstatus;
;;;1037   }
00003a  bd10              POP      {r4,pc}
;;;1038   
                          ENDP

                  |L12.60|
                          DCD      0x40026410
                  |L12.64|
                          DCD      0x40026000
                  |L12.68|
                          DCD      0x0f7d0f7d

                          AREA ||i.DMA_GetITStatus||, CODE, READONLY, ALIGN=2

                  DMA_GetITStatus PROC
;;;1151     */
;;;1152   ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
000000  b530              PUSH     {r4,r5,lr}
;;;1153   {
000002  4602              MOV      r2,r0
;;;1154     ITStatus bitstatus = RESET;
000004  2000              MOVS     r0,#0
;;;1155     DMA_TypeDef* DMAy;
;;;1156     uint32_t tmpreg = 0, enablestatus = 0;
000006  2400              MOVS     r4,#0
000008  4684              MOV      r12,r0
;;;1157   
;;;1158     /* Check the parameters */
;;;1159     assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;1160     assert_param(IS_DMA_GET_IT(DMA_IT));
;;;1161    
;;;1162     /* Determine the DMA to which belongs the stream */
;;;1163     if (DMAy_Streamx < DMA2_Stream0)
00000a  4d12              LDR      r5,|L13.84|
00000c  42aa              CMP      r2,r5
00000e  d201              BCS      |L13.20|
;;;1164     {
;;;1165       /* DMAy_Streamx belongs to DMA1 */
;;;1166       DMAy = DMA1; 
000010  4b11              LDR      r3,|L13.88|
000012  e001              B        |L13.24|
                  |L13.20|
;;;1167     } 
;;;1168     else 
;;;1169     {
;;;1170       /* DMAy_Streamx belongs to DMA2 */
;;;1171       DMAy = DMA2; 
000014  4b0f              LDR      r3,|L13.84|
000016  3b10              SUBS     r3,r3,#0x10
                  |L13.24|
;;;1172     }
;;;1173   
;;;1174     /* Check if the interrupt enable bit is in the CR or FCR register */
;;;1175     if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
000018  4d10              LDR      r5,|L13.92|
00001a  4229              TST      r1,r5
00001c  d006              BEQ      |L13.44|
;;;1176     {
;;;1177       /* Get the interrupt enable position mask in CR register */
;;;1178       tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);   
00001e  251e              MOVS     r5,#0x1e
000020  ea0524d1          AND      r4,r5,r1,LSR #11
;;;1179       
;;;1180       /* Check the enable bit in CR register */
;;;1181       enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
000024  6815              LDR      r5,[r2,#0]
000026  ea050c04          AND      r12,r5,r4
00002a  e002              B        |L13.50|
                  |L13.44|
;;;1182     }
;;;1183     else 
;;;1184     {
;;;1185       /* Check the enable bit in FCR register */
;;;1186       enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); 
00002c  6955              LDR      r5,[r2,#0x14]
00002e  f0050c80          AND      r12,r5,#0x80
                  |L13.50|
;;;1187     }
;;;1188    
;;;1189     /* Check if the interrupt pending flag is in LISR or HISR */
;;;1190     if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
000032  f0115f00          TST      r1,#0x20000000
000036  d001              BEQ      |L13.60|
;;;1191     {
;;;1192       /* Get DMAy HISR register value */
;;;1193       tmpreg = DMAy->HISR ;
000038  685c              LDR      r4,[r3,#4]
00003a  e000              B        |L13.62|
                  |L13.60|
;;;1194     }
;;;1195     else
;;;1196     {
;;;1197       /* Get DMAy LISR register value */
;;;1198       tmpreg = DMAy->LISR ;
00003c  681c              LDR      r4,[r3,#0]
                  |L13.62|
;;;1199     } 
;;;1200   
;;;1201     /* mask all reserved bits */
;;;1202     tmpreg &= (uint32_t)RESERVED_MASK;
00003e  4d08              LDR      r5,|L13.96|
000040  402c              ANDS     r4,r4,r5
;;;1203   
;;;1204     /* Check the status of the specified DMA interrupt */
;;;1205     if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
000042  420c              TST      r4,r1
000044  d004              BEQ      |L13.80|
000046  f1bc0f00          CMP      r12,#0
00004a  d001              BEQ      |L13.80|
;;;1206     {
;;;1207       /* DMA_IT is set */
;;;1208       bitstatus = SET;
00004c  2001              MOVS     r0,#1
00004e  e000              B        |L13.82|
                  |L13.80|
;;;1209     }
;;;1210     else
;;;1211     {
;;;1212       /* DMA_IT is reset */
;;;1213       bitstatus = RESET;
000050  2000              MOVS     r0,#0
                  |L13.82|
;;;1214     }
;;;1215   
;;;1216     /* Return the DMA_IT status */
;;;1217     return  bitstatus;
;;;1218   }
000052  bd30              POP      {r4,r5,pc}
;;;1219   
                          ENDP

                  |L13.84|
                          DCD      0x40026410
                  |L13.88|
                          DCD      0x40026000
                  |L13.92|
                          DCD      0x0f3c0f3c
                  |L13.96|
                          DCD      0x0f7d0f7d

                          AREA ||i.DMA_ITConfig||, CODE, READONLY, ALIGN=1

                  DMA_ITConfig PROC
;;;1099     */
;;;1100   void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
000000  b510              PUSH     {r4,lr}
;;;1101   {
;;;1102     /* Check the parameters */
;;;1103     assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;1104     assert_param(IS_DMA_CONFIG_IT(DMA_IT));
;;;1105     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1106   
;;;1107     /* Check if the DMA_IT parameter contains a FIFO interrupt */
;;;1108     if ((DMA_IT & DMA_IT_FE) != 0)
000002  f0110f80          TST      r1,#0x80
000006  d009              BEQ      |L14.28|
;;;1109     {
;;;1110       if (NewState != DISABLE)
000008  b122              CBZ      r2,|L14.20|
;;;1111       {
;;;1112         /* Enable the selected DMA FIFO interrupts */
;;;1113         DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE;
00000a  6943              LDR      r3,[r0,#0x14]
00000c  f0430380          ORR      r3,r3,#0x80
000010  6143              STR      r3,[r0,#0x14]
000012  e003              B        |L14.28|
                  |L14.20|
;;;1114       }    
;;;1115       else 
;;;1116       {
;;;1117         /* Disable the selected DMA FIFO interrupts */
;;;1118         DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE;  
000014  6943              LDR      r3,[r0,#0x14]
000016  f0230380          BIC      r3,r3,#0x80
00001a  6143              STR      r3,[r0,#0x14]
                  |L14.28|
;;;1119       }
;;;1120     }
;;;1121   
;;;1122     /* Check if the DMA_IT parameter contains a Transfer interrupt */
;;;1123     if (DMA_IT != DMA_IT_FE)
00001c  2980              CMP      r1,#0x80
00001e  d00b              BEQ      |L14.56|
;;;1124     {
;;;1125       if (NewState != DISABLE)
000020  b12a              CBZ      r2,|L14.46|
;;;1126       {
;;;1127         /* Enable the selected DMA transfer interrupts */
;;;1128         DMAy_Streamx->CR |= (uint32_t)(DMA_IT  & TRANSFER_IT_ENABLE_MASK);
000022  6803              LDR      r3,[r0,#0]
000024  f001041e          AND      r4,r1,#0x1e
000028  4323              ORRS     r3,r3,r4
00002a  6003              STR      r3,[r0,#0]
00002c  e004              B        |L14.56|
                  |L14.46|
;;;1129       }
;;;1130       else
;;;1131       {
;;;1132         /* Disable the selected DMA transfer interrupts */
;;;1133         DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
00002e  6803              LDR      r3,[r0,#0]
000030  f001041e          AND      r4,r1,#0x1e
000034  43a3              BICS     r3,r3,r4
000036  6003              STR      r3,[r0,#0]
                  |L14.56|
;;;1134       }    
;;;1135     }
;;;1136   }
000038  bd10              POP      {r4,pc}
;;;1137   
                          ENDP


                          AREA ||i.DMA_Init||, CODE, READONLY, ALIGN=2

                  DMA_Init PROC
;;;310      */
;;;311    void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct)
000000  b510              PUSH     {r4,lr}
;;;312    {
;;;313      uint32_t tmpreg = 0;
000002  2200              MOVS     r2,#0
;;;314    
;;;315      /* Check the parameters */
;;;316      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;317      assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel));
;;;318      assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR));
;;;319      assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
;;;320      assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
;;;321      assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
;;;322      assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
;;;323      assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
;;;324      assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
;;;325      assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
;;;326      assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode));
;;;327      assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold));
;;;328      assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst));
;;;329      assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst));
;;;330    
;;;331      /*------------------------- DMAy Streamx CR Configuration ------------------*/
;;;332      /* Get the DMAy_Streamx CR value */
;;;333      tmpreg = DMAy_Streamx->CR;
000004  6802              LDR      r2,[r0,#0]
;;;334    
;;;335      /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
;;;336      tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
000006  4b13              LDR      r3,|L15.84|
000008  401a              ANDS     r2,r2,r3
;;;337                             DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
;;;338                             DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
;;;339                             DMA_SxCR_DIR));
;;;340    
;;;341      /* Configure DMAy Streamx: */
;;;342      /* Set CHSEL bits according to DMA_CHSEL value */
;;;343      /* Set DIR bits according to DMA_DIR value */
;;;344      /* Set PINC bit according to DMA_PeripheralInc value */
;;;345      /* Set MINC bit according to DMA_MemoryInc value */
;;;346      /* Set PSIZE bits according to DMA_PeripheralDataSize value */
;;;347      /* Set MSIZE bits according to DMA_MemoryDataSize value */
;;;348      /* Set CIRC bit according to DMA_Mode value */
;;;349      /* Set PL bits according to DMA_Priority value */
;;;350      /* Set MBURST bits according to DMA_MemoryBurst value */
;;;351      /* Set PBURST bits according to DMA_PeripheralBurst value */
;;;352      tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
00000a  68cc              LDR      r4,[r1,#0xc]
00000c  680b              LDR      r3,[r1,#0]
00000e  4323              ORRS     r3,r3,r4
000010  694c              LDR      r4,[r1,#0x14]
000012  4323              ORRS     r3,r3,r4
000014  698c              LDR      r4,[r1,#0x18]
000016  4323              ORRS     r3,r3,r4
000018  69cc              LDR      r4,[r1,#0x1c]
00001a  4323              ORRS     r3,r3,r4
00001c  6a0c              LDR      r4,[r1,#0x20]
00001e  4323              ORRS     r3,r3,r4
000020  6a4c              LDR      r4,[r1,#0x24]
000022  4323              ORRS     r3,r3,r4
000024  6a8c              LDR      r4,[r1,#0x28]
000026  4323              ORRS     r3,r3,r4
000028  6b4c              LDR      r4,[r1,#0x34]
00002a  4323              ORRS     r3,r3,r4
00002c  6b8c              LDR      r4,[r1,#0x38]
00002e  4323              ORRS     r3,r3,r4
000030  431a              ORRS     r2,r2,r3
;;;353                DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
;;;354                DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
;;;355                DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
;;;356                DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
;;;357    
;;;358      /* Write to DMAy Streamx CR register */
;;;359      DMAy_Streamx->CR = tmpreg;
000032  6002              STR      r2,[r0,#0]
;;;360    
;;;361      /*------------------------- DMAy Streamx FCR Configuration -----------------*/
;;;362      /* Get the DMAy_Streamx FCR value */
;;;363      tmpreg = DMAy_Streamx->FCR;
000034  6942              LDR      r2,[r0,#0x14]
;;;364    
;;;365      /* Clear DMDIS and FTH bits */
;;;366      tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
000036  f0220207          BIC      r2,r2,#7
;;;367    
;;;368      /* Configure DMAy Streamx FIFO: 
;;;369        Set DMDIS bits according to DMA_FIFOMode value 
;;;370        Set FTH bits according to DMA_FIFOThreshold value */
;;;371      tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
00003a  e9d1340b          LDRD     r3,r4,[r1,#0x2c]
00003e  4323              ORRS     r3,r3,r4
000040  431a              ORRS     r2,r2,r3
;;;372    
;;;373      /* Write to DMAy Streamx CR */
;;;374      DMAy_Streamx->FCR = tmpreg;
000042  6142              STR      r2,[r0,#0x14]
;;;375    
;;;376      /*------------------------- DMAy Streamx NDTR Configuration ----------------*/
;;;377      /* Write to DMAy Streamx NDTR register */
;;;378      DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
000044  690b              LDR      r3,[r1,#0x10]
000046  6043              STR      r3,[r0,#4]
;;;379    
;;;380      /*------------------------- DMAy Streamx PAR Configuration -----------------*/
;;;381      /* Write to DMAy Streamx PAR */
;;;382      DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
000048  684b              LDR      r3,[r1,#4]
00004a  6083              STR      r3,[r0,#8]
;;;383    
;;;384      /*------------------------- DMAy Streamx M0AR Configuration ----------------*/
;;;385      /* Write to DMAy Streamx M0AR */
;;;386      DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
00004c  688b              LDR      r3,[r1,#8]
00004e  60c3              STR      r3,[r0,#0xc]
;;;387    }
000050  bd10              POP      {r4,pc}
;;;388    
                          ENDP

000052  0000              DCW      0x0000
                  |L15.84|
                          DCD      0xf01c803f

                          AREA ||i.DMA_MemoryTargetConfig||, CODE, READONLY, ALIGN=1

                  DMA_MemoryTargetConfig PROC
;;;789      */
;;;790    void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
000000  b10a              CBZ      r2,|L16.6|
;;;791                               uint32_t DMA_MemoryTarget)
;;;792    {
;;;793      /* Check the parameters */
;;;794      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;795      assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
;;;796        
;;;797      /* Check the Memory target to be configured */
;;;798      if (DMA_MemoryTarget != DMA_Memory_0)
;;;799      {
;;;800        /* Write to DMAy Streamx M1AR */
;;;801        DMAy_Streamx->M1AR = MemoryBaseAddr;    
000002  6101              STR      r1,[r0,#0x10]
000004  e000              B        |L16.8|
                  |L16.6|
;;;802      }  
;;;803      else
;;;804      {
;;;805        /* Write to DMAy Streamx M0AR */
;;;806        DMAy_Streamx->M0AR = MemoryBaseAddr;  
000006  60c1              STR      r1,[r0,#0xc]
                  |L16.8|
;;;807      }
;;;808    }
000008  4770              BX       lr
;;;809    
                          ENDP


                          AREA ||i.DMA_PeriphIncOffsetSizeConfig||, CODE, READONLY, ALIGN=1

                  DMA_PeriphIncOffsetSizeConfig PROC
;;;505      */
;;;506    void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos)
000000  b121              CBZ      r1,|L17.12|
;;;507    {
;;;508      /* Check the parameters */
;;;509      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;510      assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
;;;511    
;;;512      /* Check the needed Peripheral increment offset */
;;;513      if(DMA_Pincos != DMA_PINCOS_Psize)
;;;514      {
;;;515        /* Configure DMA_SxCR_PINCOS bit with the input parameter */
;;;516        DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS;     
000002  6802              LDR      r2,[r0,#0]
000004  f4424200          ORR      r2,r2,#0x8000
000008  6002              STR      r2,[r0,#0]
00000a  e003              B        |L17.20|
                  |L17.12|
;;;517      }
;;;518      else
;;;519      {
;;;520        /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
;;;521        DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS;    
00000c  6802              LDR      r2,[r0,#0]
00000e  f4224200          BIC      r2,r2,#0x8000
000012  6002              STR      r2,[r0,#0]
                  |L17.20|
;;;522      }
;;;523    }
000014  4770              BX       lr
;;;524    
                          ENDP


                          AREA ||i.DMA_SetCurrDataCounter||, CODE, READONLY, ALIGN=1

                  DMA_SetCurrDataCounter PROC
;;;625      */
;;;626    void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)
000000  6041              STR      r1,[r0,#4]
;;;627    {
;;;628      /* Check the parameters */
;;;629      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;630    
;;;631      /* Write the number of data units to be transferred */
;;;632      DMAy_Streamx->NDTR = (uint16_t)Counter;
;;;633    }
000002  4770              BX       lr
;;;634    
                          ENDP


                          AREA ||i.DMA_StructInit||, CODE, READONLY, ALIGN=1

                  DMA_StructInit PROC
;;;394      */
;;;395    void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
000000  2100              MOVS     r1,#0
;;;396    {
;;;397      /*-------------- Reset DMA init structure parameters values ----------------*/
;;;398      /* Initialize the DMA_Channel member */
;;;399      DMA_InitStruct->DMA_Channel = 0;
000002  6001              STR      r1,[r0,#0]
;;;400    
;;;401      /* Initialize the DMA_PeripheralBaseAddr member */
;;;402      DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
000004  6041              STR      r1,[r0,#4]
;;;403    
;;;404      /* Initialize the DMA_Memory0BaseAddr member */
;;;405      DMA_InitStruct->DMA_Memory0BaseAddr = 0;
000006  6081              STR      r1,[r0,#8]
;;;406    
;;;407      /* Initialize the DMA_DIR member */
;;;408      DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
000008  60c1              STR      r1,[r0,#0xc]
;;;409    
;;;410      /* Initialize the DMA_BufferSize member */
;;;411      DMA_InitStruct->DMA_BufferSize = 0;
00000a  6101              STR      r1,[r0,#0x10]
;;;412    
;;;413      /* Initialize the DMA_PeripheralInc member */
;;;414      DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00000c  6141              STR      r1,[r0,#0x14]
;;;415    
;;;416      /* Initialize the DMA_MemoryInc member */
;;;417      DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
00000e  6181              STR      r1,[r0,#0x18]
;;;418    
;;;419      /* Initialize the DMA_PeripheralDataSize member */
;;;420      DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
000010  61c1              STR      r1,[r0,#0x1c]
;;;421    
;;;422      /* Initialize the DMA_MemoryDataSize member */
;;;423      DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
000012  6201              STR      r1,[r0,#0x20]
;;;424    
;;;425      /* Initialize the DMA_Mode member */
;;;426      DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
000014  6241              STR      r1,[r0,#0x24]
;;;427    
;;;428      /* Initialize the DMA_Priority member */
;;;429      DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
000016  6281              STR      r1,[r0,#0x28]
;;;430    
;;;431      /* Initialize the DMA_FIFOMode member */
;;;432      DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
000018  62c1              STR      r1,[r0,#0x2c]
;;;433    
;;;434      /* Initialize the DMA_FIFOThreshold member */
;;;435      DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
00001a  6301              STR      r1,[r0,#0x30]
;;;436    
;;;437      /* Initialize the DMA_MemoryBurst member */
;;;438      DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
00001c  6341              STR      r1,[r0,#0x34]
;;;439    
;;;440      /* Initialize the DMA_PeripheralBurst member */
;;;441      DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
00001e  6381              STR      r1,[r0,#0x38]
;;;442    }
000020  4770              BX       lr
;;;443    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_dma.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_stm32f4xx_dma_c_e9b554c0____REV16|
#line 114 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f4xx_dma_c_e9b554c0____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_stm32f4xx_dma_c_e9b554c0____REVSH|
#line 128
|__asm___15_stm32f4xx_dma_c_e9b554c0____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
