; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\STM324xG_EVAL\stm32f4xx_dac.o --asm_dir=.\STM324xG_EVAL\ --list_dir=.\STM324xG_EVAL\ --depend=.\STM324xG_EVAL\stm32f4xx_dac.d --cpu=Cortex-M4.fp --apcs=interwork -O0 -Otime -I..\ -I..\..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\..\Utilities\STM32_EVAL\Common -I..\..\..\Utilities\STM32_EVAL\STM3240_41_G_EVAL -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F4xx -D__MICROLIB -DUSE_STM324xG_EVAL -DSTM32F4XX -DUSE_STDPERIPH_DRIVER --omf_browse=.\STM324xG_EVAL\stm32f4xx_dac.crf ..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dac.c]
                          THUMB

                          AREA ||i.DAC_ClearFlag||, CODE, READONLY, ALIGN=2

                  DAC_ClearFlag PROC
;;;611      */
;;;612    void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
000000  fa01f200          LSL      r2,r1,r0
;;;613    {
;;;614      /* Check the parameters */
;;;615      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;616      assert_param(IS_DAC_FLAG(DAC_FLAG));
;;;617    
;;;618      /* Clear the selected DAC flags */
;;;619      DAC->SR = (DAC_FLAG << DAC_Channel);
000004  4b01              LDR      r3,|L1.12|
000006  601a              STR      r2,[r3,#0]
;;;620    }
000008  4770              BX       lr
;;;621    
                          ENDP

00000a  0000              DCW      0x0000
                  |L1.12|
                          DCD      0x40007434

                          AREA ||i.DAC_ClearITPendingBit||, CODE, READONLY, ALIGN=2

                  DAC_ClearITPendingBit PROC
;;;674      */
;;;675    void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
000000  fa01f200          LSL      r2,r1,r0
;;;676    {
;;;677      /* Check the parameters */
;;;678      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;679      assert_param(IS_DAC_IT(DAC_IT)); 
;;;680    
;;;681      /* Clear the selected DAC interrupt pending bits */
;;;682      DAC->SR = (DAC_IT << DAC_Channel);
000004  4b01              LDR      r3,|L2.12|
000006  601a              STR      r2,[r3,#0]
;;;683    }
000008  4770              BX       lr
;;;684    
                          ENDP

00000a  0000              DCW      0x0000
                  |L2.12|
                          DCD      0x40007434

                          AREA ||i.DAC_Cmd||, CODE, READONLY, ALIGN=2

                  DAC_Cmd PROC
;;;252      */
;;;253    void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
000000  b139              CBZ      r1,|L3.18|
;;;254    {
;;;255      /* Check the parameters */
;;;256      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;257      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;258    
;;;259      if (NewState != DISABLE)
;;;260      {
;;;261        /* Enable the selected DAC channel */
;;;262        DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
000002  4a08              LDR      r2,|L3.36|
000004  6812              LDR      r2,[r2,#0]
000006  2301              MOVS     r3,#1
000008  4083              LSLS     r3,r3,r0
00000a  431a              ORRS     r2,r2,r3
00000c  4b05              LDR      r3,|L3.36|
00000e  601a              STR      r2,[r3,#0]
000010  e006              B        |L3.32|
                  |L3.18|
;;;263      }
;;;264      else
;;;265      {
;;;266        /* Disable the selected DAC channel */
;;;267        DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
000012  4a04              LDR      r2,|L3.36|
000014  6812              LDR      r2,[r2,#0]
000016  2301              MOVS     r3,#1
000018  4083              LSLS     r3,r3,r0
00001a  439a              BICS     r2,r2,r3
00001c  4b01              LDR      r3,|L3.36|
00001e  601a              STR      r2,[r3,#0]
                  |L3.32|
;;;268      }
;;;269    }
000020  4770              BX       lr
;;;270    
                          ENDP

000022  0000              DCW      0x0000
                  |L3.36|
                          DCD      0x40007400

                          AREA ||i.DAC_DMACmd||, CODE, READONLY, ALIGN=2

                  DAC_DMACmd PROC
;;;496      */
;;;497    void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
000000  b141              CBZ      r1,|L4.20|
;;;498    {
;;;499      /* Check the parameters */
;;;500      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;501      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;502    
;;;503      if (NewState != DISABLE)
;;;504      {
;;;505        /* Enable the selected DAC channel DMA request */
;;;506        DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
000002  4a09              LDR      r2,|L4.40|
000004  6812              LDR      r2,[r2,#0]
000006  f44f5380          MOV      r3,#0x1000
00000a  4083              LSLS     r3,r3,r0
00000c  431a              ORRS     r2,r2,r3
00000e  4b06              LDR      r3,|L4.40|
000010  601a              STR      r2,[r3,#0]
000012  e007              B        |L4.36|
                  |L4.20|
;;;507      }
;;;508      else
;;;509      {
;;;510        /* Disable the selected DAC channel DMA request */
;;;511        DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
000014  4a04              LDR      r2,|L4.40|
000016  6812              LDR      r2,[r2,#0]
000018  f44f5380          MOV      r3,#0x1000
00001c  4083              LSLS     r3,r3,r0
00001e  439a              BICS     r2,r2,r3
000020  4b01              LDR      r3,|L4.40|
000022  601a              STR      r2,[r3,#0]
                  |L4.36|
;;;512      }
;;;513    }
000024  4770              BX       lr
;;;514    /**
                          ENDP

000026  0000              DCW      0x0000
                  |L4.40|
                          DCD      0x40007400

                          AREA ||i.DAC_DeInit||, CODE, READONLY, ALIGN=1

                  DAC_DeInit PROC
;;;173      */
;;;174    void DAC_DeInit(void)
000000  b510              PUSH     {r4,lr}
;;;175    {
;;;176      /* Enable DAC reset state */
;;;177      RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
000002  2101              MOVS     r1,#1
000004  0748              LSLS     r0,r1,#29
000006  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;178      /* Release DAC from reset state */
;;;179      RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
00000a  2100              MOVS     r1,#0
00000c  f04f5000          MOV      r0,#0x20000000
000010  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;180    }
000014  bd10              POP      {r4,pc}
;;;181    
                          ENDP


                          AREA ||i.DAC_DualSoftwareTriggerCmd||, CODE, READONLY, ALIGN=2

                  DAC_DualSoftwareTriggerCmd PROC
;;;304      */
;;;305    void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
000000  b130              CBZ      r0,|L6.16|
;;;306    {
;;;307      /* Check the parameters */
;;;308      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;309    
;;;310      if (NewState != DISABLE)
;;;311      {
;;;312        /* Enable software trigger for both DAC channels */
;;;313        DAC->SWTRIGR |= DUAL_SWTRIG_SET;
000002  4907              LDR      r1,|L6.32|
000004  6809              LDR      r1,[r1,#0]
000006  f0410103          ORR      r1,r1,#3
00000a  4a05              LDR      r2,|L6.32|
00000c  6011              STR      r1,[r2,#0]
00000e  e005              B        |L6.28|
                  |L6.16|
;;;314      }
;;;315      else
;;;316      {
;;;317        /* Disable software trigger for both DAC channels */
;;;318        DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
000010  4903              LDR      r1,|L6.32|
000012  6809              LDR      r1,[r1,#0]
000014  f0210103          BIC      r1,r1,#3
000018  4a01              LDR      r2,|L6.32|
00001a  6011              STR      r1,[r2,#0]
                  |L6.28|
;;;319      }
;;;320    }
00001c  4770              BX       lr
;;;321    
                          ENDP

00001e  0000              DCW      0x0000
                  |L6.32|
                          DCD      0x40007404

                          AREA ||i.DAC_GetDataOutputValue||, CODE, READONLY, ALIGN=2

                  DAC_GetDataOutputValue PROC
;;;451      */
;;;452    uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
000000  4601              MOV      r1,r0
;;;453    {
;;;454      __IO uint32_t tmp = 0;
000002  2200              MOVS     r2,#0
;;;455      
;;;456      /* Check the parameters */
;;;457      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;458      
;;;459      tmp = (uint32_t) DAC_BASE ;
000004  4a03              LDR      r2,|L7.20|
;;;460      tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
000006  202c              MOVS     r0,#0x2c
000008  eb000091          ADD      r0,r0,r1,LSR #2
00000c  4402              ADD      r2,r2,r0
;;;461      
;;;462      /* Returns the DAC channel data output register value */
;;;463      return (uint16_t) (*(__IO uint32_t*) tmp);
00000e  6810              LDR      r0,[r2,#0]
000010  b280              UXTH     r0,r0
;;;464    }
000012  4770              BX       lr
;;;465    /**
                          ENDP

                  |L7.20|
                          DCD      0x40007400

                          AREA ||i.DAC_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  DAC_GetFlagStatus PROC
;;;576      */
;;;577    FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
000000  b510              PUSH     {r4,lr}
;;;578    {
000002  4602              MOV      r2,r0
;;;579      FlagStatus bitstatus = RESET;
000004  2000              MOVS     r0,#0
;;;580      /* Check the parameters */
;;;581      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;582      assert_param(IS_DAC_FLAG(DAC_FLAG));
;;;583    
;;;584      /* Check the status of the specified DAC flag */
;;;585      if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
000006  4b05              LDR      r3,|L8.28|
000008  681b              LDR      r3,[r3,#0]
00000a  fa01f402          LSL      r4,r1,r2
00000e  4223              TST      r3,r4
000010  d001              BEQ      |L8.22|
;;;586      {
;;;587        /* DAC_FLAG is set */
;;;588        bitstatus = SET;
000012  2001              MOVS     r0,#1
000014  e000              B        |L8.24|
                  |L8.22|
;;;589      }
;;;590      else
;;;591      {
;;;592        /* DAC_FLAG is reset */
;;;593        bitstatus = RESET;
000016  2000              MOVS     r0,#0
                  |L8.24|
;;;594      }
;;;595      /* Return the DAC_FLAG status */
;;;596      return  bitstatus;
;;;597    }
000018  bd10              POP      {r4,pc}
;;;598    
                          ENDP

00001a  0000              DCW      0x0000
                  |L8.28|
                          DCD      0x40007434

                          AREA ||i.DAC_GetITStatus||, CODE, READONLY, ALIGN=2

                  DAC_GetITStatus PROC
;;;634      */
;;;635    ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
000000  b530              PUSH     {r4,r5,lr}
;;;636    {
000002  4602              MOV      r2,r0
;;;637      ITStatus bitstatus = RESET;
000004  2000              MOVS     r0,#0
;;;638      uint32_t enablestatus = 0;
000006  2300              MOVS     r3,#0
;;;639      
;;;640      /* Check the parameters */
;;;641      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;642      assert_param(IS_DAC_IT(DAC_IT));
;;;643    
;;;644      /* Get the DAC_IT enable bit status */
;;;645      enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
000008  4c08              LDR      r4,|L9.44|
00000a  6824              LDR      r4,[r4,#0]
00000c  fa01f502          LSL      r5,r1,r2
000010  ea040305          AND      r3,r4,r5
;;;646      
;;;647      /* Check the status of the specified DAC interrupt */
;;;648      if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
000014  4c05              LDR      r4,|L9.44|
000016  3434              ADDS     r4,r4,#0x34
000018  6824              LDR      r4,[r4,#0]
00001a  fa01f502          LSL      r5,r1,r2
00001e  422c              TST      r4,r5
000020  d002              BEQ      |L9.40|
000022  b10b              CBZ      r3,|L9.40|
;;;649      {
;;;650        /* DAC_IT is set */
;;;651        bitstatus = SET;
000024  2001              MOVS     r0,#1
000026  e000              B        |L9.42|
                  |L9.40|
;;;652      }
;;;653      else
;;;654      {
;;;655        /* DAC_IT is reset */
;;;656        bitstatus = RESET;
000028  2000              MOVS     r0,#0
                  |L9.42|
;;;657      }
;;;658      /* Return the DAC_IT status */
;;;659      return  bitstatus;
;;;660    }
00002a  bd30              POP      {r4,r5,pc}
;;;661    
                          ENDP

                  |L9.44|
                          DCD      0x40007400

                          AREA ||i.DAC_ITConfig||, CODE, READONLY, ALIGN=2

                  DAC_ITConfig PROC
;;;544      */ 
;;;545    void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
000000  b510              PUSH     {r4,lr}
;;;546    {
;;;547      /* Check the parameters */
;;;548      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;549      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;550      assert_param(IS_DAC_IT(DAC_IT)); 
;;;551    
;;;552      if (NewState != DISABLE)
000002  b13a              CBZ      r2,|L10.20|
;;;553      {
;;;554        /* Enable the selected DAC interrupts */
;;;555        DAC->CR |=  (DAC_IT << DAC_Channel);
000004  4b07              LDR      r3,|L10.36|
000006  681b              LDR      r3,[r3,#0]
000008  fa01f400          LSL      r4,r1,r0
00000c  4323              ORRS     r3,r3,r4
00000e  4c05              LDR      r4,|L10.36|
000010  6023              STR      r3,[r4,#0]
000012  e006              B        |L10.34|
                  |L10.20|
;;;556      }
;;;557      else
;;;558      {
;;;559        /* Disable the selected DAC interrupts */
;;;560        DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
000014  4b03              LDR      r3,|L10.36|
000016  681b              LDR      r3,[r3,#0]
000018  fa01f400          LSL      r4,r1,r0
00001c  43a3              BICS     r3,r3,r4
00001e  4c01              LDR      r4,|L10.36|
000020  6023              STR      r3,[r4,#0]
                  |L10.34|
;;;561      }
;;;562    }
000022  bd10              POP      {r4,pc}
;;;563    
                          ENDP

                  |L10.36|
                          DCD      0x40007400

                          AREA ||i.DAC_Init||, CODE, READONLY, ALIGN=2

                  DAC_Init PROC
;;;192      */
;;;193    void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;194    {
;;;195      uint32_t tmpreg1 = 0, tmpreg2 = 0;
000002  2200              MOVS     r2,#0
000004  2300              MOVS     r3,#0
;;;196    
;;;197      /* Check the DAC parameters */
;;;198      assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
;;;199      assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
;;;200      assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
;;;201      assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
;;;202    
;;;203    /*---------------------------- DAC CR Configuration --------------------------*/
;;;204      /* Get the DAC CR value */
;;;205      tmpreg1 = DAC->CR;
000006  4c0a              LDR      r4,|L11.48|
000008  6822              LDR      r2,[r4,#0]
;;;206      /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
;;;207      tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
00000a  f64074fe          MOV      r4,#0xffe
00000e  4084              LSLS     r4,r4,r0
000010  43a2              BICS     r2,r2,r4
;;;208      /* Configure for the selected DAC channel: buffer output, trigger, 
;;;209         wave generation, mask/amplitude for wave generation */
;;;210      /* Set TSELx and TENx bits according to DAC_Trigger value */
;;;211      /* Set WAVEx bits according to DAC_WaveGeneration value */
;;;212      /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
;;;213      /* Set BOFFx bit according to DAC_OutputBuffer value */   
;;;214      tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
000012  e9d14500          LDRD     r4,r5,[r1,#0]
000016  432c              ORRS     r4,r4,r5
000018  688d              LDR      r5,[r1,#8]
00001a  432c              ORRS     r4,r4,r5
00001c  68cd              LDR      r5,[r1,#0xc]
00001e  ea440305          ORR      r3,r4,r5
;;;215                 DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
;;;216                 DAC_InitStruct->DAC_OutputBuffer);
;;;217      /* Calculate CR register value depending on DAC_Channel */
;;;218      tmpreg1 |= tmpreg2 << DAC_Channel;
000022  fa03f400          LSL      r4,r3,r0
000026  4322              ORRS     r2,r2,r4
;;;219      /* Write to DAC CR */
;;;220      DAC->CR = tmpreg1;
000028  4c01              LDR      r4,|L11.48|
00002a  6022              STR      r2,[r4,#0]
;;;221    }
00002c  bd30              POP      {r4,r5,pc}
;;;222    
                          ENDP

00002e  0000              DCW      0x0000
                  |L11.48|
                          DCD      0x40007400

                          AREA ||i.DAC_SetChannel1Data||, CODE, READONLY, ALIGN=2

                  DAC_SetChannel1Data PROC
;;;364      */
;;;365    void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
000000  2200              MOVS     r2,#0
;;;366    {  
;;;367      __IO uint32_t tmp = 0;
;;;368      
;;;369      /* Check the parameters */
;;;370      assert_param(IS_DAC_ALIGN(DAC_Align));
;;;371      assert_param(IS_DAC_DATA(Data));
;;;372      
;;;373      tmp = (uint32_t)DAC_BASE; 
000002  4a03              LDR      r2,|L12.16|
;;;374      tmp += DHR12R1_OFFSET + DAC_Align;
000004  f1000308          ADD      r3,r0,#8
000008  441a              ADD      r2,r2,r3
;;;375    
;;;376      /* Set the DAC channel1 selected data holding register */
;;;377      *(__IO uint32_t *) tmp = Data;
00000a  6011              STR      r1,[r2,#0]
;;;378    }
00000c  4770              BX       lr
;;;379    
                          ENDP

00000e  0000              DCW      0x0000
                  |L12.16|
                          DCD      0x40007400

                          AREA ||i.DAC_SetChannel2Data||, CODE, READONLY, ALIGN=2

                  DAC_SetChannel2Data PROC
;;;389      */
;;;390    void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
000000  2200              MOVS     r2,#0
;;;391    {
;;;392      __IO uint32_t tmp = 0;
;;;393    
;;;394      /* Check the parameters */
;;;395      assert_param(IS_DAC_ALIGN(DAC_Align));
;;;396      assert_param(IS_DAC_DATA(Data));
;;;397      
;;;398      tmp = (uint32_t)DAC_BASE;
000002  4a03              LDR      r2,|L13.16|
;;;399      tmp += DHR12R2_OFFSET + DAC_Align;
000004  f1000314          ADD      r3,r0,#0x14
000008  441a              ADD      r2,r2,r3
;;;400    
;;;401      /* Set the DAC channel2 selected data holding register */
;;;402      *(__IO uint32_t *)tmp = Data;
00000a  6011              STR      r1,[r2,#0]
;;;403    }
00000c  4770              BX       lr
;;;404    
                          ENDP

00000e  0000              DCW      0x0000
                  |L13.16|
                          DCD      0x40007400

                          AREA ||i.DAC_SetDualChannelData||, CODE, READONLY, ALIGN=2

                  DAC_SetDualChannelData PROC
;;;417      */
;;;418    void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
000000  b510              PUSH     {r4,lr}
;;;419    {
;;;420      uint32_t data = 0, tmp = 0;
000002  f04f0c00          MOV      r12,#0
000006  2300              MOVS     r3,#0
;;;421      
;;;422      /* Check the parameters */
;;;423      assert_param(IS_DAC_ALIGN(DAC_Align));
;;;424      assert_param(IS_DAC_DATA(Data1));
;;;425      assert_param(IS_DAC_DATA(Data2));
;;;426      
;;;427      /* Calculate and set dual DAC data holding register value */
;;;428      if (DAC_Align == DAC_Align_8b_R)
000008  2808              CMP      r0,#8
00000a  d102              BNE      |L14.18|
;;;429      {
;;;430        data = ((uint32_t)Data2 << 8) | Data1; 
00000c  ea422c01          ORR      r12,r2,r1,LSL #8
000010  e001              B        |L14.22|
                  |L14.18|
;;;431      }
;;;432      else
;;;433      {
;;;434        data = ((uint32_t)Data2 << 16) | Data1;
000012  ea424c01          ORR      r12,r2,r1,LSL #16
                  |L14.22|
;;;435      }
;;;436      
;;;437      tmp = (uint32_t)DAC_BASE;
000016  4b03              LDR      r3,|L14.36|
;;;438      tmp += DHR12RD_OFFSET + DAC_Align;
000018  f1000420          ADD      r4,r0,#0x20
00001c  4423              ADD      r3,r3,r4
;;;439    
;;;440      /* Set the dual DAC selected data holding register */
;;;441      *(__IO uint32_t *)tmp = data;
00001e  f8c3c000          STR      r12,[r3,#0]
;;;442    }
000022  bd10              POP      {r4,pc}
;;;443    
                          ENDP

                  |L14.36|
                          DCD      0x40007400

                          AREA ||i.DAC_SoftwareTriggerCmd||, CODE, READONLY, ALIGN=2

                  DAC_SoftwareTriggerCmd PROC
;;;280      */
;;;281    void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
000000  b510              PUSH     {r4,lr}
;;;282    {
;;;283      /* Check the parameters */
;;;284      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;285      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;286    
;;;287      if (NewState != DISABLE)
000002  b141              CBZ      r1,|L15.22|
;;;288      {
;;;289        /* Enable software trigger for the selected DAC channel */
;;;290        DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
000004  4a08              LDR      r2,|L15.40|
000006  6812              LDR      r2,[r2,#0]
000008  0904              LSRS     r4,r0,#4
00000a  2301              MOVS     r3,#1
00000c  40a3              LSLS     r3,r3,r4
00000e  431a              ORRS     r2,r2,r3
000010  4b05              LDR      r3,|L15.40|
000012  601a              STR      r2,[r3,#0]
000014  e007              B        |L15.38|
                  |L15.22|
;;;291      }
;;;292      else
;;;293      {
;;;294        /* Disable software trigger for the selected DAC channel */
;;;295        DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
000016  4a04              LDR      r2,|L15.40|
000018  6812              LDR      r2,[r2,#0]
00001a  0904              LSRS     r4,r0,#4
00001c  2301              MOVS     r3,#1
00001e  40a3              LSLS     r3,r3,r4
000020  439a              BICS     r2,r2,r3
000022  4b01              LDR      r3,|L15.40|
000024  601a              STR      r2,[r3,#0]
                  |L15.38|
;;;296      }
;;;297    }
000026  bd10              POP      {r4,pc}
;;;298    
                          ENDP

                  |L15.40|
                          DCD      0x40007404

                          AREA ||i.DAC_StructInit||, CODE, READONLY, ALIGN=1

                  DAC_StructInit PROC
;;;228      */
;;;229    void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
000000  2100              MOVS     r1,#0
;;;230    {
;;;231    /*--------------- Reset DAC init structure parameters values -----------------*/
;;;232      /* Initialize the DAC_Trigger member */
;;;233      DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
000002  6001              STR      r1,[r0,#0]
;;;234      /* Initialize the DAC_WaveGeneration member */
;;;235      DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
000004  6041              STR      r1,[r0,#4]
;;;236      /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
;;;237      DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
000006  6081              STR      r1,[r0,#8]
;;;238      /* Initialize the DAC_OutputBuffer member */
;;;239      DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
000008  60c1              STR      r1,[r0,#0xc]
;;;240    }
00000a  4770              BX       lr
;;;241    
                          ENDP


                          AREA ||i.DAC_WaveGenerationCmd||, CODE, READONLY, ALIGN=2

                  DAC_WaveGenerationCmd PROC
;;;335      */
;;;336    void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
000000  b510              PUSH     {r4,lr}
;;;337    {
;;;338      /* Check the parameters */
;;;339      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;340      assert_param(IS_DAC_WAVE(DAC_Wave)); 
;;;341      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;342    
;;;343      if (NewState != DISABLE)
000002  b13a              CBZ      r2,|L17.20|
;;;344      {
;;;345        /* Enable the selected wave generation for the selected DAC channel */
;;;346        DAC->CR |= DAC_Wave << DAC_Channel;
000004  4b07              LDR      r3,|L17.36|
000006  681b              LDR      r3,[r3,#0]
000008  fa01f400          LSL      r4,r1,r0
00000c  4323              ORRS     r3,r3,r4
00000e  4c05              LDR      r4,|L17.36|
000010  6023              STR      r3,[r4,#0]
000012  e006              B        |L17.34|
                  |L17.20|
;;;347      }
;;;348      else
;;;349      {
;;;350        /* Disable the selected wave generation for the selected DAC channel */
;;;351        DAC->CR &= ~(DAC_Wave << DAC_Channel);
000014  4b03              LDR      r3,|L17.36|
000016  681b              LDR      r3,[r3,#0]
000018  fa01f400          LSL      r4,r1,r0
00001c  43a3              BICS     r3,r3,r4
00001e  4c01              LDR      r4,|L17.36|
000020  6023              STR      r3,[r4,#0]
                  |L17.34|
;;;352      }
;;;353    }
000022  bd10              POP      {r4,pc}
;;;354    
                          ENDP

                  |L17.36|
                          DCD      0x40007400

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_dac.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_stm32f4xx_dac_c_4da4a0a9____REV16|
#line 114 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f4xx_dac_c_4da4a0a9____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_stm32f4xx_dac_c_4da4a0a9____REVSH|
#line 128
|__asm___15_stm32f4xx_dac_c_4da4a0a9____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
