; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\STM324xG_EVAL\misc.o --asm_dir=.\STM324xG_EVAL\ --list_dir=.\STM324xG_EVAL\ --depend=.\STM324xG_EVAL\misc.d --cpu=Cortex-M4.fp --apcs=interwork -O0 -Otime -I..\ -I..\..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\..\Utilities\STM32_EVAL\Common -I..\..\..\Utilities\STM32_EVAL\STM3240_41_G_EVAL -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F4xx -D__MICROLIB -DUSE_STM324xG_EVAL -DSTM32F4XX -DUSE_STDPERIPH_DRIVER --omf_browse=.\STM324xG_EVAL\misc.crf ..\..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\misc.c]
                          THUMB

                          AREA ||i.NVIC_Init||, CODE, READONLY, ALIGN=2

                  NVIC_Init PROC
;;;129      */
;;;130    void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
000000  b570              PUSH     {r4-r6,lr}
;;;131    {
;;;132      uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
000002  2100              MOVS     r1,#0
000004  2300              MOVS     r3,#0
000006  220f              MOVS     r2,#0xf
;;;133      
;;;134      /* Check the parameters */
;;;135      assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
;;;136      assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
;;;137      assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
;;;138        
;;;139      if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
000008  78c4              LDRB     r4,[r0,#3]
00000a  b324              CBZ      r4,|L1.86|
;;;140      {
;;;141        /* Compute the Corresponding IRQ Priority --------------------------------*/    
;;;142        tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
00000c  4c17              LDR      r4,|L1.108|
00000e  6824              LDR      r4,[r4,#0]
000010  f40464e0          AND      r4,r4,#0x700
000014  f5c464e0          RSB      r4,r4,#0x700
000018  f3c42107          UBFX     r1,r4,#8,#8
;;;143        tmppre = (0x4 - tmppriority);
00001c  f1c10404          RSB      r4,r1,#4
000020  b2e3              UXTB     r3,r4
;;;144        tmpsub = tmpsub >> tmppriority;
000022  410a              ASRS     r2,r2,r1
;;;145    
;;;146        tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
000024  7844              LDRB     r4,[r0,#1]
000026  409c              LSLS     r4,r4,r3
000028  b2e1              UXTB     r1,r4
;;;147        tmppriority |=  (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
00002a  7884              LDRB     r4,[r0,#2]
00002c  4014              ANDS     r4,r4,r2
00002e  4321              ORRS     r1,r1,r4
;;;148            
;;;149        tmppriority = tmppriority << 0x04;
000030  070c              LSLS     r4,r1,#28
000032  0e21              LSRS     r1,r4,#24
;;;150            
;;;151        NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
000034  4c0e              LDR      r4,|L1.112|
000036  7805              LDRB     r5,[r0,#0]
000038  5561              STRB     r1,[r4,r5]
;;;152        
;;;153        /* Enable the Selected IRQ Channels --------------------------------------*/
;;;154        NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
00003a  7804              LDRB     r4,[r0,#0]
00003c  f004051f          AND      r5,r4,#0x1f
000040  2401              MOVS     r4,#1
000042  40ac              LSLS     r4,r4,r5
000044  7805              LDRB     r5,[r0,#0]
000046  116d              ASRS     r5,r5,#5
000048  f04f26e0          MOV      r6,#0xe000e000
00004c  eb060585          ADD      r5,r6,r5,LSL #2
000050  f8c54100          STR      r4,[r5,#0x100]
000054  e009              B        |L1.106|
                  |L1.86|
;;;155          (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
;;;156      }
;;;157      else
;;;158      {
;;;159        /* Disable the Selected IRQ Channels -------------------------------------*/
;;;160        NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
000056  7804              LDRB     r4,[r0,#0]
000058  f004051f          AND      r5,r4,#0x1f
00005c  2401              MOVS     r4,#1
00005e  40ac              LSLS     r4,r4,r5
000060  4d04              LDR      r5,|L1.116|
000062  7806              LDRB     r6,[r0,#0]
000064  1176              ASRS     r6,r6,#5
000066  f8454026          STR      r4,[r5,r6,LSL #2]
                  |L1.106|
;;;161          (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
;;;162      }
;;;163    }
00006a  bd70              POP      {r4-r6,pc}
;;;164    
                          ENDP

                  |L1.108|
                          DCD      0xe000ed0c
                  |L1.112|
                          DCD      0xe000e400
                  |L1.116|
                          DCD      0xe000e180

                          AREA ||i.NVIC_PriorityGroupConfig||, CODE, READONLY, ALIGN=2

                  NVIC_PriorityGroupConfig PROC
;;;111      */
;;;112    void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
000000  4902              LDR      r1,|L2.12|
;;;113    {
;;;114      /* Check the parameters */
;;;115      assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
;;;116      
;;;117      /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
;;;118      SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
000002  4301              ORRS     r1,r1,r0
000004  4a02              LDR      r2,|L2.16|
000006  6011              STR      r1,[r2,#0]
;;;119    }
000008  4770              BX       lr
;;;120    
                          ENDP

00000a  0000              DCW      0x0000
                  |L2.12|
                          DCD      0x05fa0000
                  |L2.16|
                          DCD      0xe000ed0c

                          AREA ||i.NVIC_SetVectorTable||, CODE, READONLY, ALIGN=2

                  NVIC_SetVectorTable PROC
;;;173      */
;;;174    void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
000000  4a02              LDR      r2,|L3.12|
;;;175    { 
;;;176      /* Check the parameters */
;;;177      assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
;;;178      assert_param(IS_NVIC_OFFSET(Offset));  
;;;179       
;;;180      SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
000002  400a              ANDS     r2,r2,r1
000004  4302              ORRS     r2,r2,r0
000006  4b02              LDR      r3,|L3.16|
000008  601a              STR      r2,[r3,#0]
;;;181    }
00000a  4770              BX       lr
;;;182    
                          ENDP

                  |L3.12|
                          DCD      0x1fffff80
                  |L3.16|
                          DCD      0xe000ed08

                          AREA ||i.NVIC_SystemLPConfig||, CODE, READONLY, ALIGN=2

                  NVIC_SystemLPConfig PROC
;;;192      */
;;;193    void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
000000  b129              CBZ      r1,|L4.14|
;;;194    {
;;;195      /* Check the parameters */
;;;196      assert_param(IS_NVIC_LP(LowPowerMode));
;;;197      assert_param(IS_FUNCTIONAL_STATE(NewState));  
;;;198      
;;;199      if (NewState != DISABLE)
;;;200      {
;;;201        SCB->SCR |= LowPowerMode;
000002  4a06              LDR      r2,|L4.28|
000004  6812              LDR      r2,[r2,#0]
000006  4302              ORRS     r2,r2,r0
000008  4b04              LDR      r3,|L4.28|
00000a  601a              STR      r2,[r3,#0]
00000c  e004              B        |L4.24|
                  |L4.14|
;;;202      }
;;;203      else
;;;204      {
;;;205        SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
00000e  4a03              LDR      r2,|L4.28|
000010  6812              LDR      r2,[r2,#0]
000012  4382              BICS     r2,r2,r0
000014  4b01              LDR      r3,|L4.28|
000016  601a              STR      r2,[r3,#0]
                  |L4.24|
;;;206      }
;;;207    }
000018  4770              BX       lr
;;;208    
                          ENDP

00001a  0000              DCW      0x0000
                  |L4.28|
                          DCD      0xe000ed10

                          AREA ||i.SysTick_CLKSourceConfig||, CODE, READONLY, ALIGN=1

                  SysTick_CLKSourceConfig PROC
;;;216      */
;;;217    void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
000000  2804              CMP      r0,#4
;;;218    {
;;;219      /* Check the parameters */
;;;220      assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
;;;221      if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
000002  d108              BNE      |L5.22|
;;;222      {
;;;223        SysTick->CTRL |= SysTick_CLKSource_HCLK;
000004  f04f21e0          MOV      r1,#0xe000e000
000008  6909              LDR      r1,[r1,#0x10]
00000a  f0410104          ORR      r1,r1,#4
00000e  f04f22e0          MOV      r2,#0xe000e000
000012  6111              STR      r1,[r2,#0x10]
000014  e007              B        |L5.38|
                  |L5.22|
;;;224      }
;;;225      else
;;;226      {
;;;227        SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
000016  f04f21e0          MOV      r1,#0xe000e000
00001a  6909              LDR      r1,[r1,#0x10]
00001c  f0210104          BIC      r1,r1,#4
000020  f04f22e0          MOV      r2,#0xe000e000
000024  6111              STR      r1,[r2,#0x10]
                  |L5.38|
;;;228      }
;;;229    }
000026  4770              BX       lr
;;;230    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\misc.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___6_misc_c_d0fc1254____REV16|
#line 114 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___6_misc_c_d0fc1254____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___6_misc_c_d0fc1254____REVSH|
#line 128
|__asm___6_misc_c_d0fc1254____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
